aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-09-04debug: Add first cut to call compliance testscompliance_testsMegan Wachs1-0/+26
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
Only works against spike, where I've implemented some custom debug registers to test against.
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful.
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
@timsifive we are debugging intermittent failures.
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome2-3/+4
2018-08-23Get all of the log into the final log fileTim Newsome1-6/+20
This allows me to see the final valgrind output on OpenOCD, so I can watch for memory leaks when using --server_cmd "valgrind --leak-check=full openocd".
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
Add debug test, which checks that openocd correctly switch active thread on any hart halt.
2018-08-22Merge branch 'master' of https://github.com/riscv/riscv-testsTim Newsome1-2/+2
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification
2018-08-22Add debug test, which checks that openocd correctly switch active thread on ↵Dmitry Ryzhov1-0/+28
any hart halt.
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
The mstatus reading overwrites the expected user mode cause value.
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves.
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use.
2018-06-18Add reproduce line to the end of debug test logsTim Newsome1-0/+2
2018-05-21Merge pull request #141 from riscv/mrhstestTim Newsome2-23/+46
Fix MulticoreRunHaltStepiTest
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome2-23/+46
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so.
2018-05-15Merge pull request #139 from riscv/debug-tests-more-singleMegan Wachs2-10/+19
Mark more Debug tests as "Single Hart"
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs2-21/+11
2018-05-14Make DownloadTest properly park other harts.Tim Newsome2-5/+9
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-05-11debug: output some more useful info into the post-mortem dataMegan Wachs1-0/+5
2018-04-30[rv64ua/lrsc] Initialize memory read out. (#135)Christopher Celio1-1/+3
* [rv64ua/lrsc] Initialize memory read out. Even though the load contents are discarded, this un-initialized memory value can lead to a divergence for co-simulation between two different RISC-V designs. * [rv64ua/lrsc] Use .skip instead of .align.
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-28Merge pull request #132 from riscv/debug-clear-satpMegan Wachs1-0/+7
debug: need to clear satp before changing priv
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
2018-04-27Merge pull request #125 from riscv/debug-delete-simMegan Wachs1-17/+0
Delete E300Sim.py
2018-04-27Merge pull request #130 from riscv/trap_entry_align-1Megan Wachs1-0/+1
debug: add missing align directive on trap_entry
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-04-24Fix race when making logs directoryTim Newsome1-1/+5
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
This file is wrong (the .cfg file isn't right) and not used by anything.
2018-04-16Merge pull request #123 from riscv/gdb_timeoutTim Newsome2-14/+18
Compute gdb command timeout based on ops estimate
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome2-14/+18
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122.
2018-04-09Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)Andrei Tatarnikov1-3/+3
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome4-3/+19
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-23Print log filename at the end of the log.Tim Newsome1-0/+1
This makes it much easier to look at a log if you see a failure scrolling by on your terminal.
2018-03-21Make misa.C test conform to Hauser proposalAndrew Waterman1-43/+10
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7
2018-03-20Merge pull request #119 from rishikhan/masterPalmer Dabbelt1-2/+8
Update Makefile to allow for RISCV_PREFIX to be set by the configure
2018-03-19Update Makefile to allow for RISCV_PREFIX to be set by the configure --targetrishi1-2/+8
2018-03-01Test debugging with/without a program bufferTim Newsome5-5/+10
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome5-0/+29
2018-02-27Add test for clearing misa.C while PC is misaligned (#117)Andrew Waterman1-1/+79
See https://github.com/riscv/riscv-isa-manual/pull/139
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome3-10/+9
generated by cgit v1.1 at 2024-07-17 01:05:00 +0000