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2022-11-29Check basic debugging still works in CeaseMulticeasetest2Tim Newsome1-6/+18
2022-11-29Raise UnknownThread in select_hart()Tim Newsome1-1/+7
2022-11-29When parking harts, use `cease` if it's supported.Tim Newsome1-2/+8
This is a much more comprehensive test of OpenOCD behavior when harts become unavailable.
2022-11-29Move exit() into GdbTest().Tim Newsome3-16/+9
2022-11-29Add `support_cease` hart feature.Tim Newsome2-3/+6
2022-11-29Make CeaseMultiTest do something reasonable.Tim Newsome1-8/+12
2022-11-29Add precease sectionTim Newsome1-0/+7
2022-11-29Create CeaseRunSingleTestTim Newsome1-0/+22
2022-11-29Make new cease testTim Newsome1-4/+5
2022-11-29Create CeaseSingleTest.Tim Newsome1-2/+26
2022-11-29Add Gdb.expect()Tim Newsome1-0/+3
2022-11-29Add wait argument to stepi()Tim Newsome1-3/+7
2022-11-29Recognize gdb "Could not read registers" error message.Tim Newsome1-0/+7
2022-11-29Add CeaseTestTim Newsome3-2/+34
To test OpenOCD behavior when one or more harts are powered down.
2022-11-29Recognize gdb "No registers." error message.Tim Newsome1-0/+5
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
Also change the test itself to require less RAM than it did previously. (It had required more than 32KB.)
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
It would fail intermittently. We can't guarantee all harts resume simultaneously. When we let multiple harts run to a breakpoint at the end of the same loop, one is likely to get there first, and the second won't make it. To avoid this problem, run for a short amount of time instead of to a breakpoint.
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
Before it might fail incorrectly, because main was close to trap_entry.
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
* Specify trigger type=2 in trigger.S Previous tests implicitly assume triggers only support type=2. However, a trigger may support multiple types, i.e., type=15. This commit explicitly specifies type=2 in trigger.S to support type 15. * Update debug/programs/trigger.S Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
Between October 13 and October 19, something happened that makes the multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or riscv-tests doesn't affect this. Presumably it's due to a kernel or python change in my Ubuntu system. I don't have time to look at this right now, so just increase the timeouts. :-( If I had to guess, there could be a bug in rbb_daisychain.py that wastes a lot of time.
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests.
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
Fix long line to make pylint happy.
2022-10-20Merge pull request #420 from riscv-software-src/test_fpr_progbufTim Newsome3-2/+9
Get coverage of progbuf FPR accesses.
2022-10-12Fix long line to make pylint happy.Tim Newsome1-1/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome3-2/+9
Using the new spike support merged in https://github.com/riscv-software-src/riscv-isa-sim/pull/1109
2022-10-10Merge pull request #417 from riscv-software-src/debug_serverTim Newsome2-3/+14
debug: Add --debug_server arg to open gdb on OpenOCD
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome2-3/+14
Not as useful as I'd like because we don't connect until after examine() has completed, and the test is likely to time out while debugging. But good to have, and maybe I'll expand on it one day.
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
update gdbserver.py; tolerance value of MemorySampleTest()
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
The control sequences (^[[?2004h and ^[[?2004l) occur after the gdb.command, which results in Exception fault. This commit removes the control sequences and strips out the blank lines (^M).
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
These can change at any time and that is OK.
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
I don't have time to fix the bug right now, and nobody has run into the bug yet in any case.
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
Turn semihosting_fileio on for every hart. This test still fails if it ends up running on hart 1 instead of 0, but at least it's closer to passing. Feels like the remaining problem is in OpenOCD.
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
* Another pylint upgrade. Lots of format string changes, which are more readable. More files to come... * Satisfy pylint for two more files.
2022-06-21Update information about Makefile fragments (#399)Mehmet Oguz Derin1-4/+2
The source of benchmarks' Makefile does not use fragments anymore. This commit removes the mention of them from the readme. Signed-off-by: Mehmet Oguz Derin <mehmetoguzderin@mehmetoguzderin.com>
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
2022-06-08Merge pull request #395 from riscv-software-src/misaligned_storeAndrew Waterman10-6/+164
Test misaligned stores
2022-06-08Test semihosting_fileioTim Newsome2-4/+27
In the original test, confirm that stdout data ends up in the OpenOCD log. In the new test, with `arm semihosting_fileio` enabled, confirm that stdout data ends up in gdb's CLI. This test requires https://github.com/riscv/riscv-openocd/pull/699.
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
Cover lh, lw, and ld (only on rv64).
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior.
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
They lead to two problems: 1. The change to set TESTNUM before the test instead of after broke a few tests that relied on the old behavior. 2. Some tests in the v variant do something in the exception handler such that when they get an unaligned access exception, they end up stuck in a loop of unaligned access exceptions and the exception handler set up in the test is never called.
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
Identical to the lw change in #391.
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
The test passes if either the target register contains the correct value, or the target raises a misaligned load exception.
generated by cgit v1.1 at 2024-06-29 04:34:51 +0000