diff options
Diffstat (limited to 'isa/rv64ui/srl.S')
| -rw-r--r-- | isa/rv64ui/srl.S | 75 |
1 files changed, 39 insertions, 36 deletions
diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S index 876c303..ad5c2e5 100644 --- a/isa/rv64ui/srl.S +++ b/isa/rv64ui/srl.S @@ -17,23 +17,26 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_RR_OP( 2, srl, 0xffffffff80000000, 0xffffffff80000000, 0 ); - TEST_RR_OP( 3, srl, 0x7fffffffc0000000, 0xffffffff80000000, 1 ); - TEST_RR_OP( 4, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_OP( 5, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_OP( 6, srl, 0x00000001ffffffff, 0xffffffff80000001, 31 ); - - TEST_RR_OP( 7, srl, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); - TEST_RR_OP( 8, srl, 0x7fffffffffffffff, 0xffffffffffffffff, 1 ); - TEST_RR_OP( 9, srl, 0x01ffffffffffffff, 0xffffffffffffffff, 7 ); - TEST_RR_OP( 10, srl, 0x0003ffffffffffff, 0xffffffffffffffff, 14 ); - TEST_RR_OP( 11, srl, 0x00000001ffffffff, 0xffffffffffffffff, 31 ); - - TEST_RR_OP( 12, srl, 0x0000000021212121, 0x0000000021212121, 0 ); - TEST_RR_OP( 13, srl, 0x0000000010909090, 0x0000000021212121, 1 ); - TEST_RR_OP( 14, srl, 0x0000000000424242, 0x0000000021212121, 7 ); - TEST_RR_OP( 15, srl, 0x0000000000008484, 0x0000000021212121, 14 ); - TEST_RR_OP( 16, srl, 0x0000000000000000, 0x0000000021212121, 31 ); +#define TEST_SRL(n, v, a) \ + TEST_RR_OP(n, srl, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); # Verify that shifts only use bottom five bits @@ -47,31 +50,31 @@ RVTEST_CODE_BEGIN # Source/Destination tests #------------------------------------------------------------- - TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); #------------------------------------------------------------- # Bypassing tests #------------------------------------------------------------- - TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); |