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-rw-r--r--isa/rv64mi/breakpoint.S4
-rw-r--r--isa/rv64mi/ma_addr.S4
-rw-r--r--isa/rv64mi/mcsr.S2
3 files changed, 5 insertions, 5 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index b318c30..ba683cc 100644
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN
# Make sure there's a breakpoint there.
csrr a0, tdata1
- srli a0, a0, _RISCV_SZLONG-4
+ srli a0, a0, __riscv_xlen - 4
li a1, 2
bne a0, a1, pass
@@ -90,7 +90,7 @@ RVTEST_CODE_BEGIN
# Make sure there's a breakpoint there.
csrr a0, tdata1
- srli a0, a0, _RISCV_SZLONG-4
+ srli a0, a0, __riscv_xlen - 4
li a1, 2
bne a0, a1, pass
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 6e7be94..be3572f 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -31,7 +31,7 @@ RVTEST_CODE_BEGIN
MISALIGNED_LDST_TEST(5, lw, s0, 2)
MISALIGNED_LDST_TEST(6, lw, s0, 3)
-#ifdef __riscv64
+#if __riscv_xlen == 64
MISALIGNED_LDST_TEST(7, lwu, s0, 1)
MISALIGNED_LDST_TEST(8, lwu, s0, 2)
MISALIGNED_LDST_TEST(9, lwu, s0, 3)
@@ -53,7 +53,7 @@ RVTEST_CODE_BEGIN
MISALIGNED_LDST_TEST(24, sw, s0, 2)
MISALIGNED_LDST_TEST(25, sw, s0, 3)
-#ifdef __riscv64
+#if __riscv_xlen == 64
MISALIGNED_LDST_TEST(26, sd, s0, 1)
MISALIGNED_LDST_TEST(27, sd, s0, 2)
MISALIGNED_LDST_TEST(28, sd, s0, 3)
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index b66611c..e0256e7 100644
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -14,7 +14,7 @@ RVTEST_RV64M
RVTEST_CODE_BEGIN
# Check that mcpuid reports the correct XLEN
-#ifdef __riscv64
+#if __riscv_xlen == 64
TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
#else
TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)