diff options
Diffstat (limited to 'debug/targets/RISC-V')
-rw-r--r-- | debug/targets/RISC-V/spike-multi.py | 22 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike32.py | 4 | ||||
-rw-r--r-- | debug/targets/RISC-V/spike64.py | 5 |
3 files changed, 9 insertions, 22 deletions
diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py index 9e85a35..816677b 100644 --- a/debug/targets/RISC-V/spike-multi.py +++ b/debug/targets/RISC-V/spike-multi.py @@ -2,16 +2,14 @@ import targets import testlib import spike32 # pylint: disable=import-error -#import spike64 # pylint: disable=import-error +import spike64 # pylint: disable=import-error class multispike(targets.Target): harts = [ spike32.spike32_hart(misa=0x4034112d, system=0), spike32.spike32_hart(misa=0x4034112d, system=0), - spike32.spike32_hart(misa=0x4034112d, system=1), - spike32.spike32_hart(misa=0x4034112d, system=1)] - #spike64.spike64_hart(misa=0x8000000000341129), - #spike64.spike64_hart(misa=0x8000000000341129)] + spike64.spike64_hart(misa=0x8000000000341129, system=1), + spike64.spike64_hart(misa=0x8000000000341129, system=1)] openocd_config_path = "spike-multi.cfg" # Increased timeout because we use abstract_rti to artificially slow things # down. @@ -25,15 +23,11 @@ class multispike(targets.Target): # requires vlen==slen. return testlib.MultiSpike( [ -# testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, -# support_hasel=False, support_abstract_csr=False, -# vlen=512, elen=64, slen=512, harts=self.harts[:2]), - testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4, + testlib.Spike(self, isa="RV64IMAFDV", + support_hasel=False, support_abstract_csr=False, + vlen=512, elen=64, slen=512, harts=self.harts[2:]), + testlib.Spike(self, isa="RV32IMAFDCV", support_abstract_csr=True, support_haltgroups=False, # elen must be at least 64 because D is supported. - elen=64, harts=self.harts[2:]), - testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4, - support_abstract_csr=True, support_haltgroups=False, - # elen must be at least 64 because D is supported. - elen=64, harts=self.harts[2:]) + elen=64, harts=self.harts[:2]), ]) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 6256574..17d28fb 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -10,10 +10,6 @@ class spike32_hart(targets.Hart): reset_vectors = [0x1000] link_script_path = "spike32.lds" - def __init__(self, misa, system=0): - super().__init__(system=system) - self.misa = misa - class spike32(targets.Target): harts = [spike32_hart(misa=0x4034112d)] openocd_config_path = "spike-1.cfg" diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 4313968..31088ff 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -9,10 +9,7 @@ class spike64_hart(targets.Hart): instruction_hardware_breakpoint_count = 4 reset_vectors = [0x1000] link_script_path = "spike64.lds" - - def __init__(self, misa=0x8000000000141125, system=0): - super().__init__(system=system) - self.misa = misa + misa = 0x8000000000141125 class spike64(targets.Target): harts = [spike64_hart()] |