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-rw-r--r--debug/targets/RISC-V/spike-multi.py4
1 files changed, 1 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py
index 816677b..82de76f 100644
--- a/debug/targets/RISC-V/spike-multi.py
+++ b/debug/targets/RISC-V/spike-multi.py
@@ -19,13 +19,11 @@ class multispike(targets.Target):
support_memory_sampling = False # Needs SBA
def create(self):
- # TODO: It would be nice to test with slen=128, but spike currently
- # requires vlen==slen.
return testlib.MultiSpike(
[
testlib.Spike(self, isa="RV64IMAFDV",
support_hasel=False, support_abstract_csr=False,
- vlen=512, elen=64, slen=512, harts=self.harts[2:]),
+ vlen=512, elen=64, harts=self.harts[2:]),
testlib.Spike(self, isa="RV32IMAFDCV",
support_abstract_csr=True, support_haltgroups=False,
# elen must be at least 64 because D is supported.