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Diffstat (limited to 'debug/targets/RISC-V/spike-multi.py')
-rw-r--r--debug/targets/RISC-V/spike-multi.py22
1 files changed, 8 insertions, 14 deletions
diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py
index 9e85a35..816677b 100644
--- a/debug/targets/RISC-V/spike-multi.py
+++ b/debug/targets/RISC-V/spike-multi.py
@@ -2,16 +2,14 @@ import targets
import testlib
import spike32 # pylint: disable=import-error
-#import spike64 # pylint: disable=import-error
+import spike64 # pylint: disable=import-error
class multispike(targets.Target):
harts = [
spike32.spike32_hart(misa=0x4034112d, system=0),
spike32.spike32_hart(misa=0x4034112d, system=0),
- spike32.spike32_hart(misa=0x4034112d, system=1),
- spike32.spike32_hart(misa=0x4034112d, system=1)]
- #spike64.spike64_hart(misa=0x8000000000341129),
- #spike64.spike64_hart(misa=0x8000000000341129)]
+ spike64.spike64_hart(misa=0x8000000000341129, system=1),
+ spike64.spike64_hart(misa=0x8000000000341129, system=1)]
openocd_config_path = "spike-multi.cfg"
# Increased timeout because we use abstract_rti to artificially slow things
# down.
@@ -25,15 +23,11 @@ class multispike(targets.Target):
# requires vlen==slen.
return testlib.MultiSpike(
[
-# testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
-# support_hasel=False, support_abstract_csr=False,
-# vlen=512, elen=64, slen=512, harts=self.harts[:2]),
- testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4,
+ testlib.Spike(self, isa="RV64IMAFDV",
+ support_hasel=False, support_abstract_csr=False,
+ vlen=512, elen=64, slen=512, harts=self.harts[2:]),
+ testlib.Spike(self, isa="RV32IMAFDCV",
support_abstract_csr=True, support_haltgroups=False,
# elen must be at least 64 because D is supported.
- elen=64, harts=self.harts[2:]),
- testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4,
- support_abstract_csr=True, support_haltgroups=False,
- # elen must be at least 64 because D is supported.
- elen=64, harts=self.harts[2:])
+ elen=64, harts=self.harts[:2]),
])