diff options
| -rwxr-xr-x | debug/gdbserver.py | 12 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-rtos.cfg | 29 |
2 files changed, 12 insertions, 29 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 768c4c4..20c1dbe 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1660,6 +1660,18 @@ class VectorTest(GdbSingleHartTest): assertIn("Breakpoint", output) assertIn("test0", output) + # I'm not convinced that writing 0 is supported on every vector + # implementation. If this test fails, that might be why. + for regname in ('$vl', '$vtype'): + value = self.gdb.p(regname) + assertNotEqual(value, 0) + self.gdb.p("%s=0" % regname) + self.gdb.command("flushregs") + assertEqual(self.gdb.p(regname), 0) + self.gdb.p("%s=0x%x" % (regname, value)) + self.gdb.command("flushregs") + assertEqual(self.gdb.p(regname), value) + assertEqual(self.gdb.p("$a0"), 0) a = self.gdb.x("&a", 'b', vlenb) b = self.gdb.x("&b", 'b', vlenb) diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg deleted file mode 100644 index 395a9f8..0000000 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ /dev/null @@ -1,29 +0,0 @@ -# Connect to a mult-icore RISC-V target, exposing each hart as a thread. -adapter_khz 10000 - -interface remote_bitbang -remote_bitbang_host $::env(REMOTE_BITBANG_HOST) -remote_bitbang_port $::env(REMOTE_BITBANG_PORT) - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -enable_rtos_riscv - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv - -gdb_report_data_abort enable -gdb_report_register_access_error enable - -# Expose an unimplemented CSR so we can test non-existent register access -# behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 - -init - -set challenge [riscv authdata_read] -riscv authdata_write [expr $challenge + 1] - -halt |