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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-30 13:02:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-30 13:13:52 -0700 |
| commit | 8c633e9e80d0b3e3764ebc3651e9cc09ab9413c9 (patch) | |
| tree | fc8b6f6c7a2231e52e095c7a1cb682fd18f79235 /isa | |
| parent | 2a9cd2c6cc19863c781bcaa8b276de6e528fba8e (diff) | |
| download | riscv-tests-8c633e9e80d0b3e3764ebc3651e9cc09ab9413c9.zip riscv-tests-8c633e9e80d0b3e3764ebc3651e9cc09ab9413c9.tar.gz riscv-tests-8c633e9e80d0b3e3764ebc3651e9cc09ab9413c9.tar.bz2 | |
Share code between rv32ui and rv64ui tests
They were almost identical, so I made them actually identical. This
will reduce the burden of writing further tests that span base ISAs.
Tests can still be specialized for XLEN with ifdefs on e.g. __riscv64.
Diffstat (limited to 'isa')
39 files changed, 180 insertions, 2516 deletions
diff --git a/isa/rv32ui/add.S b/isa/rv32ui/add.S index 2eb330e..3ab883d 100644 --- a/isa/rv32ui/add.S +++ b/isa/rv32ui/add.S @@ -1,85 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# add.S -#----------------------------------------------------------------------------- -# -# Test add instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, add, 0xffff8000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, add, 0x80000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, add, 0x7fff8000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP( 8, add, 0x00007fff, 0x00000000, 0x00007fff ); - TEST_RR_OP( 9, add, 0x7fffffff, 0x7fffffff, 0x00000000 ); - TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff ); - - TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff ); - TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 ); - - TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff ); - TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 ); - TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff ); - - TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); - TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); - TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); - TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); - TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); - TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); - TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); - TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); - TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); - TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); - TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); - TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); - TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); - - TEST_RR_ZEROSRC1( 35, add, 15, 15 ); - TEST_RR_ZEROSRC2( 36, add, 32, 32 ); - TEST_RR_ZEROSRC12( 37, add, 0 ); - TEST_RR_ZERODEST( 38, add, 16, 30 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/add.S" diff --git a/isa/rv32ui/addi.S b/isa/rv32ui/addi.S index f7a418b..fa80a68 100644 --- a/isa/rv32ui/addi.S +++ b/isa/rv32ui/addi.S @@ -1,71 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# addi.S -#----------------------------------------------------------------------------- -# -# Test addi instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); - TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); - TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); - - TEST_IMM_OP( 5, addi, 0xfffff800, 0x00000000, 0x800 ); - TEST_IMM_OP( 6, addi, 0x80000000, 0x80000000, 0x000 ); - TEST_IMM_OP( 7, addi, 0x7ffff800, 0x80000000, 0x800 ); - - TEST_IMM_OP( 8, addi, 0x000007ff, 0x00000000, 0x7ff ); - TEST_IMM_OP( 9, addi, 0x7fffffff, 0x7fffffff, 0x000 ); - TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff ); - - TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff ); - TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 ); - - TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff ); - TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 ); - TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff ); - - TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); - TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); - TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); - - TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); - TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); - TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); - - TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); - TEST_IMM_ZERODEST( 25, addi, 33, 50 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/addi.S" diff --git a/isa/rv32ui/and.S b/isa/rv32ui/and.S index 561ae3b..4ee105b 100644 --- a/isa/rv32ui/and.S +++ b/isa/rv32ui/and.S @@ -1,69 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# and.S -#----------------------------------------------------------------------------- -# -# Test and instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); - TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); - TEST_RR_ZEROSRC12( 26, and, 0 ); - TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/and.S" diff --git a/isa/rv32ui/andi.S b/isa/rv32ui/andi.S index c2ae94d..e6b1529 100644 --- a/isa/rv32ui/andi.S +++ b/isa/rv32ui/andi.S @@ -1,55 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# andi.S -#----------------------------------------------------------------------------- -# -# Test andi instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); - TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); - TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); - TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); - TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); - - TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); - TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); - TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); - - TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); - TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/andi.S" diff --git a/isa/rv32ui/auipc.S b/isa/rv32ui/auipc.S index c67e3c9..0827f7d 100644 --- a/isa/rv32ui/auipc.S +++ b/isa/rv32ui/auipc.S @@ -1,39 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# auipc.S -#----------------------------------------------------------------------------- -# -# Test auipc instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a0, 10000, \ - .align 3; \ - lla a0, 1f + 10000; \ - jal a1, 1f; \ - 1: sub a0, a0, a1; \ - ) - - TEST_CASE(3, a0, -10000, \ - .align 3; \ - lla a0, 1f - 10000; \ - jal a1, 1f; \ - 1: sub a0, a0, a1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/auipc.S" diff --git a/isa/rv32ui/beq.S b/isa/rv32ui/beq.S index c972eff..7c3996d 100644 --- a/isa/rv32ui/beq.S +++ b/isa/rv32ui/beq.S @@ -1,73 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# beq.S -#----------------------------------------------------------------------------- -# -# Test beq instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); - TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); - TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); - - TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); - TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); - TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); - TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 21, x1, 3, \ - li x1, 1; \ - beq x0, x0, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/beq.S" diff --git a/isa/rv32ui/bge.S b/isa/rv32ui/bge.S index d6aea7c..d47c304 100644 --- a/isa/rv32ui/bge.S +++ b/isa/rv32ui/bge.S @@ -1,76 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# bge.S -#----------------------------------------------------------------------------- -# -# Test bge instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); - TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); - TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); - TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); - TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); - TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); - - TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); - TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); - TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); - TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); - - TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 24, x1, 3, \ - li x1, 1; \ - bge x1, x0, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/bge.S" diff --git a/isa/rv32ui/bgeu.S b/isa/rv32ui/bgeu.S index 114c845..560ec45 100644 --- a/isa/rv32ui/bgeu.S +++ b/isa/rv32ui/bgeu.S @@ -1,76 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# bgeu.S -#----------------------------------------------------------------------------- -# -# Test bgeu instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); - TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); - TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); - TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); - TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); - TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); - - TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); - TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); - TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); - TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); - - TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 24, x1, 3, \ - li x1, 1; \ - bgeu x1, x0, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/bgeu.S" diff --git a/isa/rv32ui/blt.S b/isa/rv32ui/blt.S index 12e28c3..72017dd 100644 --- a/isa/rv32ui/blt.S +++ b/isa/rv32ui/blt.S @@ -1,73 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# blt.S -#----------------------------------------------------------------------------- -# -# Test blt instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); - TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); - TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); - - TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); - TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); - TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); - TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 21, x1, 3, \ - li x1, 1; \ - blt x0, x1, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/blt.S" diff --git a/isa/rv32ui/bltu.S b/isa/rv32ui/bltu.S index 5dcfe7e..80f7468 100644 --- a/isa/rv32ui/bltu.S +++ b/isa/rv32ui/bltu.S @@ -1,73 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# bltu.S -#----------------------------------------------------------------------------- -# -# Test bltu instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); - TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); - TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); - - TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); - TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); - TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); - TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 21, x1, 3, \ - li x1, 1; \ - bltu x0, x1, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/bltu.S" diff --git a/isa/rv32ui/bne.S b/isa/rv32ui/bne.S index 0b33753..ddb7d9f 100644 --- a/isa/rv32ui/bne.S +++ b/isa/rv32ui/bne.S @@ -1,73 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# bne.S -#----------------------------------------------------------------------------- -# -# Test bne instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); - TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); - TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); - TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); - - TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); - TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); - TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); - - #------------------------------------------------------------- - # Test delay slot instructions not executed nor bypassed - #------------------------------------------------------------- - - TEST_CASE( 21, x1, 3, \ - li x1, 1; \ - bne x1, x0, 1f; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ - addi x1, x1, 1; \ -1: addi x1, x1, 1; \ - addi x1, x1, 1; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/bne.S" diff --git a/isa/rv32ui/lb.S b/isa/rv32ui/lb.S index eaf7902..6cf4d44 100644 --- a/isa/rv32ui/lb.S +++ b/isa/rv32ui/lb.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lb.S -#----------------------------------------------------------------------------- -# -# Test lb instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lb, 0xffffffff, 0, tdat ); - TEST_LD_OP( 3, lb, 0x00000000, 1, tdat ); - TEST_LD_OP( 4, lb, 0xfffffff0, 2, tdat ); - TEST_LD_OP( 5, lb, 0x0000000f, 3, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lb, 0xffffffff, -3, tdat4 ); - TEST_LD_OP( 7, lb, 0x00000000, -2, tdat4 ); - TEST_LD_OP( 8, lb, 0xfffffff0, -1, tdat4 ); - TEST_LD_OP( 9, lb, 0x0000000f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0xffffffff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lb x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0x00000000, \ - la x1, tdat; \ - addi x1, x1, -6; \ - lb x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffff0, 1, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lb, 0x0000000f, 1, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lb, 0x00000000, 1, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffff0, 1, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x0000000f, 1, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x00000000, 1, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lb x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lb x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .byte 0xff -tdat2: .byte 0x00 -tdat3: .byte 0xf0 -tdat4: .byte 0x0f +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lb.S" diff --git a/isa/rv32ui/lbu.S b/isa/rv32ui/lbu.S index 027b643..a479a0f 100644 --- a/isa/rv32ui/lbu.S +++ b/isa/rv32ui/lbu.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lbu.S -#----------------------------------------------------------------------------- -# -# Test lbu instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lbu, 0x000000ff, 0, tdat ); - TEST_LD_OP( 3, lbu, 0x00000000, 1, tdat ); - TEST_LD_OP( 4, lbu, 0x000000f0, 2, tdat ); - TEST_LD_OP( 5, lbu, 0x0000000f, 3, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lbu, 0x000000ff, -3, tdat4 ); - TEST_LD_OP( 7, lbu, 0x00000000, -2, tdat4 ); - TEST_LD_OP( 8, lbu, 0x000000f0, -1, tdat4 ); - TEST_LD_OP( 9, lbu, 0x0000000f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x000000ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lbu x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0x00000000, \ - la x1, tdat; \ - addi x1, x1, -6; \ - lbu x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x000000f0, 1, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x0000000f, 1, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x00000000, 1, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x000000f0, 1, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x0000000f, 1, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x00000000, 1, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lbu x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lbu x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .byte 0xff -tdat2: .byte 0x00 -tdat3: .byte 0xf0 -tdat4: .byte 0x0f +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lbu.S" diff --git a/isa/rv32ui/ld.S b/isa/rv32ui/ld.S deleted file mode 100644 index 8e24f0b..0000000 --- a/isa/rv32ui/ld.S +++ /dev/null @@ -1,92 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ld.S -#----------------------------------------------------------------------------- -# -# Test ld instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, ld, 0x00ff00ff, 0, tdat ); - TEST_LD_OP( 3, ld, 0xff00ff00, 8, tdat ); - TEST_LD_OP( 4, ld, 0x0ff00ff0, 16, tdat ); - TEST_LD_OP( 5, ld, 0xf00ff00f, 24, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, ld, 0x00ff00ff, -24, tdat4 ); - TEST_LD_OP( 7, ld, 0xff00ff00, -16, tdat4 ); - TEST_LD_OP( 8, ld, 0x0ff00ff0, -8, tdat4 ); - TEST_LD_OP( 9, ld, 0xf00ff00f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x00ff00ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - ld x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0xff00ff00, \ - la x1, tdat; \ - addi x1, x1, -3; \ - ld x3, 11(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff0, 8, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00f, 8, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00, 8, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff0, 8, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00f, 8, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00, 8, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - ld x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - ld x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .dword 0x00ff00ff -tdat2: .dword 0xff00ff00 -tdat3: .dword 0x0ff00ff0 -tdat4: .dword 0xf00ff00f - -RVTEST_DATA_END diff --git a/isa/rv32ui/lh.S b/isa/rv32ui/lh.S index d8eda91..f1b2390 100644 --- a/isa/rv32ui/lh.S +++ b/isa/rv32ui/lh.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lh.S -#----------------------------------------------------------------------------- -# -# Test lh instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lh, 0x000000ff, 0, tdat ); - TEST_LD_OP( 3, lh, 0xffffff00, 2, tdat ); - TEST_LD_OP( 4, lh, 0x00000ff0, 4, tdat ); - TEST_LD_OP( 5, lh, 0xfffff00f, 6, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lh, 0x000000ff, -6, tdat4 ); - TEST_LD_OP( 7, lh, 0xffffff00, -4, tdat4 ); - TEST_LD_OP( 8, lh, 0x00000ff0, -2, tdat4 ); - TEST_LD_OP( 9, lh, 0xfffff00f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x000000ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lh x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0xffffff00, \ - la x1, tdat; \ - addi x1, x1, -5; \ - lh x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lh, 0x00000ff0, 2, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffff00f, 2, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffff00, 2, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x00000ff0, 2, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffff00f, 2, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffff00, 2, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lh x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lh x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .half 0x00ff -tdat2: .half 0xff00 -tdat3: .half 0x0ff0 -tdat4: .half 0xf00f +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lh.S" diff --git a/isa/rv32ui/lhu.S b/isa/rv32ui/lhu.S index 71daec6..775765f 100644 --- a/isa/rv32ui/lhu.S +++ b/isa/rv32ui/lhu.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lhu.S -#----------------------------------------------------------------------------- -# -# Test lhu instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lhu, 0x000000ff, 0, tdat ); - TEST_LD_OP( 3, lhu, 0x0000ff00, 2, tdat ); - TEST_LD_OP( 4, lhu, 0x00000ff0, 4, tdat ); - TEST_LD_OP( 5, lhu, 0x0000f00f, 6, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lhu, 0x000000ff, -6, tdat4 ); - TEST_LD_OP( 7, lhu, 0x0000ff00, -4, tdat4 ); - TEST_LD_OP( 8, lhu, 0x00000ff0, -2, tdat4 ); - TEST_LD_OP( 9, lhu, 0x0000f00f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x000000ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lhu x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0x0000ff00, \ - la x1, tdat; \ - addi x1, x1, -5; \ - lhu x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x00000ff0, 2, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x0000f00f, 2, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x0000ff00, 2, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x00000ff0, 2, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x0000f00f, 2, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x0000ff00, 2, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lhu x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lhu x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .half 0x00ff -tdat2: .half 0xff00 -tdat3: .half 0x0ff0 -tdat4: .half 0xf00f +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lhu.S" diff --git a/isa/rv32ui/lui.S b/isa/rv32ui/lui.S index 50822d1..a127d61 100644 --- a/isa/rv32ui/lui.S +++ b/isa/rv32ui/lui.S @@ -1,36 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lui.S -#----------------------------------------------------------------------------- -# -# Test lui instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 ); - TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1); - TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20); - TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20); - - TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lui.S" diff --git a/isa/rv32ui/lw.S b/isa/rv32ui/lw.S index 4a07838..3b747d8 100644 --- a/isa/rv32ui/lw.S +++ b/isa/rv32ui/lw.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# lw.S -#----------------------------------------------------------------------------- -# -# Test lw instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lw, 0x00ff00ff, 0, tdat ); - TEST_LD_OP( 3, lw, 0xff00ff00, 4, tdat ); - TEST_LD_OP( 4, lw, 0x0ff00ff0, 8, tdat ); - TEST_LD_OP( 5, lw, 0xf00ff00f, 12, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lw, 0x00ff00ff, -12, tdat4 ); - TEST_LD_OP( 7, lw, 0xff00ff00, -8, tdat4 ); - TEST_LD_OP( 8, lw, 0x0ff00ff0, -4, tdat4 ); - TEST_LD_OP( 9, lw, 0xf00ff00f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x00ff00ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lw x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0xff00ff00, \ - la x1, tdat; \ - addi x1, x1, -3; \ - lw x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lw, 0x0ff00ff0, 4, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lw, 0xf00ff00f, 4, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lw, 0xff00ff00, 4, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x0ff00ff0, 4, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xf00ff00f, 4, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xff00ff00, 4, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lw x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lw x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .word 0x00ff00ff -tdat2: .word 0xff00ff00 -tdat3: .word 0x0ff00ff0 -tdat4: .word 0xf00ff00f +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/lw.S" diff --git a/isa/rv32ui/lwu.S b/isa/rv32ui/lwu.S deleted file mode 100644 index 818a257..0000000 --- a/isa/rv32ui/lwu.S +++ /dev/null @@ -1,92 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lwu.S -#----------------------------------------------------------------------------- -# -# Test lwu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_LD_OP( 2, lwu, 0x00ff00ff, 0, tdat ); - TEST_LD_OP( 3, lwu, 0xff00ff00, 4, tdat ); - TEST_LD_OP( 4, lwu, 0x0ff00ff0, 8, tdat ); - TEST_LD_OP( 5, lwu, 0xf00ff00f, 12, tdat ); - - # Test with negative offset - - TEST_LD_OP( 6, lwu, 0x00ff00ff, -12, tdat4 ); - TEST_LD_OP( 7, lwu, 0xff00ff00, -8, tdat4 ); - TEST_LD_OP( 8, lwu, 0x0ff00ff0, -4, tdat4 ); - TEST_LD_OP( 9, lwu, 0xf00ff00f, 0, tdat4 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x00ff00ff, \ - la x1, tdat; \ - addi x1, x1, -32; \ - lwu x3, 32(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0xff00ff00, \ - la x1, tdat; \ - addi x1, x1, -3; \ - lwu x3, 7(x1); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x0ff00ff0, 4, tdat2 ); - TEST_LD_DEST_BYPASS( 13, 1, lwu, 0xf00ff00f, 4, tdat3 ); - TEST_LD_DEST_BYPASS( 14, 2, lwu, 0xff00ff00, 4, tdat1 ); - - TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x0ff00ff0, 4, tdat2 ); - TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0xf00ff00f, 4, tdat3 ); - TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0xff00ff00, 4, tdat1 ); - - #------------------------------------------------------------- - # Test write-after-write hazard - #------------------------------------------------------------- - - TEST_CASE( 18, x2, 2, \ - la x3, tdat; \ - lwu x2, 0(x3); \ - li x2, 2; \ - ) - - TEST_CASE( 19, x2, 2, \ - la x3, tdat; \ - lwu x2, 0(x3); \ - nop; \ - li x2, 2; \ - ) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .word 0x00ff00ff -tdat2: .word 0xff00ff00 -tdat3: .word 0x0ff00ff0 -tdat4: .word 0xf00ff00f - -RVTEST_DATA_END diff --git a/isa/rv32ui/or.S b/isa/rv32ui/or.S index 110bcc4..1cf5674 100644 --- a/isa/rv32ui/or.S +++ b/isa/rv32ui/or.S @@ -1,69 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# or.S -#----------------------------------------------------------------------------- -# -# Test or instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); - TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); - TEST_RR_ZEROSRC12( 26, or, 0 ); - TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/or.S" diff --git a/isa/rv32ui/ori.S b/isa/rv32ui/ori.S index a674784..3399649 100644 --- a/isa/rv32ui/ori.S +++ b/isa/rv32ui/ori.S @@ -1,55 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# ori.S -#----------------------------------------------------------------------------- -# -# Test ori instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, ori, 0xffffff0f, 0xff00ff00, 0xf0f ); - TEST_IMM_OP( 3, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_OP( 4, ori, 0x00ff07ff, 0x00ff00ff, 0x70f ); - TEST_IMM_OP( 5, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x00ff07ff, 0x00ff00ff, 0x70f ); - TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffff, 0x00ff00ff, 0xf0f ); - TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); - TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/ori.S" diff --git a/isa/rv32ui/sb.S b/isa/rv32ui/sb.S index 05d1894..b2f99ac 100644 --- a/isa/rv32ui/sb.S +++ b/isa/rv32ui/sb.S @@ -1,96 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sb.S -#----------------------------------------------------------------------------- -# -# Test sb instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat ); - TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat ); - TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat ); - TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat ); - - # Test with negative offset - - TEST_ST_OP( 6, lb, sb, 0xffffffaa, -3, tdat8 ); - TEST_ST_OP( 7, lb, sb, 0x00000000, -2, tdat8 ); - TEST_ST_OP( 8, lb, sb, 0xffffffa0, -1, tdat8 ); - TEST_ST_OP( 9, lb, sb, 0x0000000a, 0, tdat8 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x78, \ - la x1, tdat9; \ - li x2, 0x12345678; \ - addi x4, x1, -32; \ - sb x2, 32(x4); \ - lb x3, 0(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0xffffff98, \ - la x1, tdat9; \ - li x2, 0x00003098; \ - addi x1, x1, -6; \ - sb x2, 7(x1); \ - la x4, tdat10; \ - lb x3, 0(x4); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffdd, 0, tdat ); - TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffcd, 1, tdat ); - TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffcc, 2, tdat ); - TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffbc, 3, tdat ); - TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffbb, 4, tdat ); - TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffab, 5, tdat ); - - TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); - TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); - TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); - TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); - TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); - TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); - - li a0, 0xef - la a1, tdat - sb a0, 3(a1) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .byte 0xef -tdat2: .byte 0xef -tdat3: .byte 0xef -tdat4: .byte 0xef -tdat5: .byte 0xef -tdat6: .byte 0xef -tdat7: .byte 0xef -tdat8: .byte 0xef -tdat9: .byte 0xef -tdat10: .byte 0xef +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sb.S" diff --git a/isa/rv32ui/sh.S b/isa/rv32ui/sh.S index 6c47274..eb5a72d 100644 --- a/isa/rv32ui/sh.S +++ b/isa/rv32ui/sh.S @@ -1,114 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sh.S -#----------------------------------------------------------------------------- -# -# Test sh instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat ); - TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat ); - TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat ); - TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat ); - - # Test with negative offset - - TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 ); - TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 ); - TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 ); - TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0, tdat8 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x5678, \ - la x1, tdat9; \ - li x2, 0x12345678; \ - addi x4, x1, -32; \ - sh x2, 32(x4); \ - lh x3, 0(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0x3098, \ - la x1, tdat9; \ - li x2, 0x00003098; \ - addi x1, x1, -5; \ - sh x2, 7(x1); \ - la x4, tdat10; \ - lh x3, 0(x4); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0, tdat ); - TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2, tdat ); - TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4, tdat ); - TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat ); - TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat ); - TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat ); - - TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); - TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); - TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); - TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); - TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); - TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); - - #--------------------------------------------------------------- - # Side effect tests - #--------------------------------------------------------------- - - # sh to a word aligned address should only affect the 2 lower bytes - # and should leave the 2 upper bytes unmodified. - # - # In this test we write 2 bytes to the lower 2 bytes of the word - # tdat11 and then ensure that the both the upper 2 bytes and - # lower 2 bytes are as expected. - TEST_CASE( 24, x3, 0x12343098, \ - la x1, tdat11; \ - li x2, 0x00003098; \ - sh x2, 0(x1); \ - lw x3, 0(x1); \ - ) - - li a0, 0xbeef - la a1, tdat - sh a0, 6(a1) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .half 0xbeef -tdat2: .half 0xbeef -tdat3: .half 0xbeef -tdat4: .half 0xbeef -tdat5: .half 0xbeef -tdat6: .half 0xbeef -tdat7: .half 0xbeef -tdat8: .half 0xbeef -tdat9: .half 0xbeef -tdat10: .half 0xbeef -tdat11: .word 0x12345678 +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sh.S" diff --git a/isa/rv32ui/simple.S b/isa/rv32ui/simple.S index 92cf203..20e5546 100644 --- a/isa/rv32ui/simple.S +++ b/isa/rv32ui/simple.S @@ -1,27 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# simple.S -#----------------------------------------------------------------------------- -# -# This is the most basic self checking test. If your simulator does not -# pass thiss then there is little chance that it will pass any of the -# more complicated self checking tests. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - -RVTEST_PASS - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/simple.S" diff --git a/isa/rv32ui/sll.S b/isa/rv32ui/sll.S index d297ac5..237df9e 100644 --- a/isa/rv32ui/sll.S +++ b/isa/rv32ui/sll.S @@ -1,90 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sll.S -#----------------------------------------------------------------------------- -# -# Test sll instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, sll, 0x00000001, 0x00000001, 0 ); - TEST_RR_OP( 3, sll, 0x00000002, 0x00000001, 1 ); - TEST_RR_OP( 4, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_OP( 5, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_OP( 6, sll, 0x80000000, 0x00000001, 31 ); - - TEST_RR_OP( 7, sll, 0xffffffff, 0xffffffff, 0 ); - TEST_RR_OP( 8, sll, 0xfffffffe, 0xffffffff, 1 ); - TEST_RR_OP( 9, sll, 0xffffff80, 0xffffffff, 7 ); - TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 ); - TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 ); - - TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0 ); - TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1 ); - TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7 ); - TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 ); - TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 ); - - # Verify that shifts only use bottom five bits - - TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 ); - TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 ); - TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 ); - TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee ); - TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 ); - - TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); - TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); - TEST_RR_ZEROSRC12( 42, sll, 0 ); - TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sll.S" diff --git a/isa/rv32ui/slli.S b/isa/rv32ui/slli.S index a51eec9..5f950e1 100644 --- a/isa/rv32ui/slli.S +++ b/isa/rv32ui/slli.S @@ -1,68 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# slli.S -#----------------------------------------------------------------------------- -# -# Test slli instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, slli, 0x00000001, 0x00000001, 0 ); - TEST_IMM_OP( 3, slli, 0x00000002, 0x00000001, 1 ); - TEST_IMM_OP( 4, slli, 0x00000080, 0x00000001, 7 ); - TEST_IMM_OP( 5, slli, 0x00004000, 0x00000001, 14 ); - TEST_IMM_OP( 6, slli, 0x80000000, 0x00000001, 31 ); - - TEST_IMM_OP( 7, slli, 0xffffffff, 0xffffffff, 0 ); - TEST_IMM_OP( 8, slli, 0xfffffffe, 0xffffffff, 1 ); - TEST_IMM_OP( 9, slli, 0xffffff80, 0xffffffff, 7 ); - TEST_IMM_OP( 10, slli, 0xffffc000, 0xffffffff, 14 ); - TEST_IMM_OP( 11, slli, 0x80000000, 0xffffffff, 31 ); - - TEST_IMM_OP( 12, slli, 0x21212121, 0x21212121, 0 ); - TEST_IMM_OP( 13, slli, 0x42424242, 0x21212121, 1 ); - TEST_IMM_OP( 14, slli, 0x90909080, 0x21212121, 7 ); - TEST_IMM_OP( 15, slli, 0x48484000, 0x21212121, 14 ); - TEST_IMM_OP( 16, slli, 0x80000000, 0x21212121, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x00000080, 0x00000001, 7 ); - TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x00004000, 0x00000001, 14 ); - TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x80000000, 0x00000001, 31 ); - - TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x00000080, 0x00000001, 7 ); - TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x00004000, 0x00000001, 14 ); - TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x80000000, 0x00000001, 31 ); - - TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); - TEST_IMM_ZERODEST( 25, slli, 33, 20 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/slli.S" diff --git a/isa/rv32ui/sra.S b/isa/rv32ui/sra.S index 8c1de36..08abe19 100644 --- a/isa/rv32ui/sra.S +++ b/isa/rv32ui/sra.S @@ -1,90 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sra.S -#----------------------------------------------------------------------------- -# -# Test sra instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, sra, 0x80000000, 0x80000000, 0 ); - TEST_RR_OP( 3, sra, 0xc0000000, 0x80000000, 1 ); - TEST_RR_OP( 4, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_OP( 5, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_OP( 6, sra, 0xffffffff, 0x80000001, 31 ); - - TEST_RR_OP( 7, sra, 0x7fffffff, 0x7fffffff, 0 ); - TEST_RR_OP( 8, sra, 0x3fffffff, 0x7fffffff, 1 ); - TEST_RR_OP( 9, sra, 0x00ffffff, 0x7fffffff, 7 ); - TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 ); - TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 ); - - TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0 ); - TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1 ); - TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7 ); - TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 ); - TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 ); - - # Verify that shifts only use bottom five bits - - TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 ); - TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 ); - TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 ); - TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce ); - TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 ); - - TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); - TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); - TEST_RR_ZEROSRC12( 42, sra, 0 ); - TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sra.S" diff --git a/isa/rv32ui/srai.S b/isa/rv32ui/srai.S index 4638190..b62a880 100644 --- a/isa/rv32ui/srai.S +++ b/isa/rv32ui/srai.S @@ -1,68 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# srai.S -#----------------------------------------------------------------------------- -# -# Test srai instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, srai, 0x00000000, 0x00000000, 0 ); - TEST_IMM_OP( 3, srai, 0xc0000000, 0x80000000, 1 ); - TEST_IMM_OP( 4, srai, 0xff000000, 0x80000000, 7 ); - TEST_IMM_OP( 5, srai, 0xfffe0000, 0x80000000, 14 ); - TEST_IMM_OP( 6, srai, 0xffffffff, 0x80000001, 31 ); - - TEST_IMM_OP( 7, srai, 0x7fffffff, 0x7fffffff, 0 ); - TEST_IMM_OP( 8, srai, 0x3fffffff, 0x7fffffff, 1 ); - TEST_IMM_OP( 9, srai, 0x00ffffff, 0x7fffffff, 7 ); - TEST_IMM_OP( 10, srai, 0x0001ffff, 0x7fffffff, 14 ); - TEST_IMM_OP( 11, srai, 0x00000000, 0x7fffffff, 31 ); - - TEST_IMM_OP( 12, srai, 0x81818181, 0x81818181, 0 ); - TEST_IMM_OP( 13, srai, 0xc0c0c0c0, 0x81818181, 1 ); - TEST_IMM_OP( 14, srai, 0xff030303, 0x81818181, 7 ); - TEST_IMM_OP( 15, srai, 0xfffe0606, 0x81818181, 14 ); - TEST_IMM_OP( 16, srai, 0xffffffff, 0x81818181, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xff000000, 0x80000000, 7 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xff000000, 0x80000000, 7 ); - TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffe0000, 0x80000000, 14 ); - TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffff, 0x80000001, 31 ); - - TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xff000000, 0x80000000, 7 ); - TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 ); - TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 ); - - TEST_IMM_ZEROSRC1( 24, srai, 0, 31 ); - TEST_IMM_ZERODEST( 25, srai, 33, 20 ); -# - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/srai.S" diff --git a/isa/rv32ui/srl.S b/isa/rv32ui/srl.S index 35cc4c7..c0ac841 100644 --- a/isa/rv32ui/srl.S +++ b/isa/rv32ui/srl.S @@ -1,90 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# srl.S -#----------------------------------------------------------------------------- -# -# Test srl instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, srl, 0xffff8000, 0xffff8000, 0 ); - TEST_RR_OP( 3, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_OP( 4, srl, 0x01ffff00, 0xffff8000, 7 ); - TEST_RR_OP( 5, srl, 0x0003fffe, 0xffff8000, 14 ); - TEST_RR_OP( 6, srl, 0x0001ffff, 0xffff8001, 15 ); - - TEST_RR_OP( 7, srl, 0xffffffff, 0xffffffff, 0 ); - TEST_RR_OP( 8, srl, 0x7fffffff, 0xffffffff, 1 ); - TEST_RR_OP( 9, srl, 0x01ffffff, 0xffffffff, 7 ); - TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 ); - TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 ); - - TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0 ); - TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1 ); - TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7 ); - TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 ); - TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 ); - - # Verify that shifts only use bottom five bits - - TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 ); - TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 ); - TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 ); - TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee ); - TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 ); - TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 ); - - TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); - TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); - TEST_RR_ZEROSRC12( 42, srl, 0 ); - TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/srl.S" diff --git a/isa/rv32ui/srli.S b/isa/rv32ui/srli.S index c2797cd..ef0203b 100644 --- a/isa/rv32ui/srli.S +++ b/isa/rv32ui/srli.S @@ -1,69 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# srli.S -#----------------------------------------------------------------------------- -# -# Test srli instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, srli, 0xffff8000, 0xffff8000, 0 ); - TEST_IMM_OP( 3, srli, 0x7fffc000, 0xffff8000, 1 ); - TEST_IMM_OP( 4, srli, 0x01ffff00, 0xffff8000, 7 ); - TEST_IMM_OP( 5, srli, 0x0003fffe, 0xffff8000, 14 ); - TEST_IMM_OP( 6, srli, 0x0001ffff, 0xffff8001, 15 ); - - TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 ); - TEST_IMM_OP( 8, srli, 0x7fffffff, 0xffffffff, 1 ); - TEST_IMM_OP( 9, srli, 0x01ffffff, 0xffffffff, 7 ); - TEST_IMM_OP( 10, srli, 0x0003ffff, 0xffffffff, 14 ); - TEST_IMM_OP( 11, srli, 0x00000001, 0xffffffff, 31 ); - - TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 ); - TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 ); - TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 ); - TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 ); - TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 21, srli, 0x7fffc000, 0xffff8000, 1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 ); - TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - - TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); - TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); - TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - - - TEST_IMM_ZEROSRC1( 28, srli, 0, 31 ); - TEST_IMM_ZERODEST( 29, srli, 33, 20 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/srli.S" diff --git a/isa/rv32ui/sub.S b/isa/rv32ui/sub.S index ad56e3e..330f478 100644 --- a/isa/rv32ui/sub.S +++ b/isa/rv32ui/sub.S @@ -1,83 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sub.S -#----------------------------------------------------------------------------- -# -# Test sub instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, sub, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, sub, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, sub, 0xfffffffc, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, sub, 0x00008000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, sub, 0x80000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, sub, 0x80008000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP( 8, sub, 0xffff8001, 0x00000000, 0x00007fff ); - TEST_RR_OP( 9, sub, 0x7fffffff, 0x7fffffff, 0x00000000 ); - TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff ); - - TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff ); - TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 ); - - TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff ); - TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 ); - TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); - TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); - TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); - TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); - TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); - TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); - TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); - TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); - TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); - TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); - TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); - TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); - TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); - - TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); - TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); - TEST_RR_ZEROSRC12( 36, sub, 0 ); - TEST_RR_ZERODEST( 37, sub, 16, 30 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sub.S" diff --git a/isa/rv32ui/sw.S b/isa/rv32ui/sw.S index fbf76cc..3098133 100644 --- a/isa/rv32ui/sw.S +++ b/isa/rv32ui/sw.S @@ -1,92 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# sw.S -#----------------------------------------------------------------------------- -# -# Test sw instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Basic tests - #------------------------------------------------------------- - - TEST_ST_OP( 2, lw, sw, 0x00aa00aa, 0, tdat ); - TEST_ST_OP( 3, lw, sw, 0xaa00aa00, 4, tdat ); - TEST_ST_OP( 4, lw, sw, 0x0aa00aa0, 8, tdat ); - TEST_ST_OP( 5, lw, sw, 0xa00aa00a, 12, tdat ); - - # Test with negative offset - - TEST_ST_OP( 6, lw, sw, 0x00aa00aa, -12, tdat8 ); - TEST_ST_OP( 7, lw, sw, 0xaa00aa00, -8, tdat8 ); - TEST_ST_OP( 8, lw, sw, 0x0aa00aa0, -4, tdat8 ); - TEST_ST_OP( 9, lw, sw, 0xa00aa00a, 0, tdat8 ); - - # Test with a negative base - - TEST_CASE( 10, x3, 0x12345678, \ - la x1, tdat9; \ - li x2, 0x12345678; \ - addi x4, x1, -32; \ - sw x2, 32(x4); \ - lw x3, 0(x1); \ - ) - - # Test with unaligned base - - TEST_CASE( 11, x3, 0x58213098, \ - la x1, tdat9; \ - li x2, 0x58213098; \ - addi x1, x1, -3; \ - sw x2, 7(x1); \ - la x4, tdat10; \ - lw x3, 0(x4); \ - ) - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xaabbccdd, 0, tdat ); - TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xdaabbccd, 4, tdat ); - TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xddaabbcc, 8, tdat ); - TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xcddaabbc, 12, tdat ); - TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xccddaabb, 16, tdat ); - TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xbccddaab, 20, tdat ); - - TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); - TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); - TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); - TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); - TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); - TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -tdat: -tdat1: .word 0xdeadbeef -tdat2: .word 0xdeadbeef -tdat3: .word 0xdeadbeef -tdat4: .word 0xdeadbeef -tdat5: .word 0xdeadbeef -tdat6: .word 0xdeadbeef -tdat7: .word 0xdeadbeef -tdat8: .word 0xdeadbeef -tdat9: .word 0xdeadbeef -tdat10: .word 0xdeadbeef +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/sw.S" diff --git a/isa/rv32ui/xor.S b/isa/rv32ui/xor.S index 72875fe..a9c1e41 100644 --- a/isa/rv32ui/xor.S +++ b/isa/rv32ui/xor.S @@ -1,69 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# xor.S -#----------------------------------------------------------------------------- -# -# Test xor instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); - TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); - TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); - - TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); - TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); - TEST_RR_ZEROSRC12( 26, xor, 0 ); - TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/xor.S" diff --git a/isa/rv32ui/xori.S b/isa/rv32ui/xori.S index 7f2207c..9e71152 100644 --- a/isa/rv32ui/xori.S +++ b/isa/rv32ui/xori.S @@ -1,55 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# xori.S -#----------------------------------------------------------------------------- -# -# Test xori instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Logical tests - #------------------------------------------------------------- - - TEST_IMM_OP( 2, xori, 0xff00f00f, 0x00ff0f00, 0xf0f ); - TEST_IMM_OP( 3, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_OP( 4, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f ); - TEST_IMM_OP( 5, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xff00f00f, 0xff00f700, 0x70f ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f ); - TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 ); - TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x00ff0ff0, 0x00ff0fff, 0x00f ); - TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 ); - - TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); - TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/xori.S" diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S index b6c2fb3..31037d1 100644 --- a/isa/rv64ui/sll.S +++ b/isa/rv64ui/sll.S @@ -41,7 +41,13 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#ifdef __riscv64 TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif #------------------------------------------------------------- # Source/Destination tests diff --git a/isa/rv64ui/slli.S b/isa/rv64ui/slli.S index fe1be59..dd02d49 100644 --- a/isa/rv64ui/slli.S +++ b/isa/rv64ui/slli.S @@ -35,6 +35,12 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); +#ifdef __riscv64 + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- @@ -53,8 +59,8 @@ RVTEST_CODE_BEGIN TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); - TEST_IMM_ZEROSRC1( 24, slli, 0, 32 ); - TEST_IMM_ZERODEST( 25, slli, 33, 50 ); + TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli, 33, 20 ); TEST_PASSFAIL diff --git a/isa/rv64ui/srai.S b/isa/rv64ui/srai.S index dff2348..8d05213 100644 --- a/isa/rv64ui/srai.S +++ b/isa/rv64ui/srai.S @@ -53,8 +53,8 @@ RVTEST_CODE_BEGIN TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); - TEST_IMM_ZEROSRC1( 24, srai, 0, 32 ); - TEST_IMM_ZERODEST( 25, srai, 33, 50 ); + TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); + TEST_IMM_ZERODEST( 25, srai, 33, 10 ); TEST_PASSFAIL diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S index 876c303..ad5c2e5 100644 --- a/isa/rv64ui/srl.S +++ b/isa/rv64ui/srl.S @@ -17,23 +17,26 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_RR_OP( 2, srl, 0xffffffff80000000, 0xffffffff80000000, 0 ); - TEST_RR_OP( 3, srl, 0x7fffffffc0000000, 0xffffffff80000000, 1 ); - TEST_RR_OP( 4, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_OP( 5, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_OP( 6, srl, 0x00000001ffffffff, 0xffffffff80000001, 31 ); - - TEST_RR_OP( 7, srl, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); - TEST_RR_OP( 8, srl, 0x7fffffffffffffff, 0xffffffffffffffff, 1 ); - TEST_RR_OP( 9, srl, 0x01ffffffffffffff, 0xffffffffffffffff, 7 ); - TEST_RR_OP( 10, srl, 0x0003ffffffffffff, 0xffffffffffffffff, 14 ); - TEST_RR_OP( 11, srl, 0x00000001ffffffff, 0xffffffffffffffff, 31 ); - - TEST_RR_OP( 12, srl, 0x0000000021212121, 0x0000000021212121, 0 ); - TEST_RR_OP( 13, srl, 0x0000000010909090, 0x0000000021212121, 1 ); - TEST_RR_OP( 14, srl, 0x0000000000424242, 0x0000000021212121, 7 ); - TEST_RR_OP( 15, srl, 0x0000000000008484, 0x0000000021212121, 14 ); - TEST_RR_OP( 16, srl, 0x0000000000000000, 0x0000000021212121, 31 ); +#define TEST_SRL(n, v, a) \ + TEST_RR_OP(n, srl, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); # Verify that shifts only use bottom five bits @@ -47,31 +50,31 @@ RVTEST_CODE_BEGIN # Source/Destination tests #------------------------------------------------------------- - TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); #------------------------------------------------------------- # Bypassing tests #------------------------------------------------------------- - TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - - TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - - TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); - TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001ffffffff, 0xffffffff80000000, 31 ); + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S index 61e5da5..eae2532 100644 --- a/isa/rv64ui/srli.S +++ b/isa/rv64ui/srli.S @@ -17,44 +17,47 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_IMM_OP( 2, srli, 0xffffffff80000000, 0xffffffff80000000, 0 ); - TEST_IMM_OP( 3, srli, 0x7fffffffc0000000, 0xffffffff80000000, 1 ); - TEST_IMM_OP( 4, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_IMM_OP( 5, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_IMM_OP( 6, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 ); - - TEST_IMM_OP( 7, srli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); - TEST_IMM_OP( 8, srli, 0x7fffffffffffffff, 0xffffffffffffffff, 1 ); - TEST_IMM_OP( 9, srli, 0x01ffffffffffffff, 0xffffffffffffffff, 7 ); - TEST_IMM_OP( 10, srli, 0x0003ffffffffffff, 0xffffffffffffffff, 14 ); - TEST_IMM_OP( 11, srli, 0x00000001ffffffff, 0xffffffffffffffff, 31 ); - - TEST_IMM_OP( 12, srli, 0x0000000021212121, 0x0000000021212121, 0 ); - TEST_IMM_OP( 13, srli, 0x0000000010909090, 0x0000000021212121, 1 ); - TEST_IMM_OP( 14, srli, 0x0000000000424242, 0x0000000021212121, 7 ); - TEST_IMM_OP( 15, srli, 0x0000000000008484, 0x0000000021212121, 14 ); - TEST_IMM_OP( 16, srli, 0x0000000000000000, 0x0000000021212121, 31 ); +#define TEST_SRL(n, v, a) \ + TEST_IMM_OP(n, srli, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- - TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); #------------------------------------------------------------- # Bypassing tests #------------------------------------------------------------- - TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 ); + TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); - TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01ffffffff000000, 0xffffffff80000000, 7 ); - TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x0003fffffffe0000, 0xffffffff80000000, 14 ); - TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001ffffffff, 0xffffffff80000001, 31 ); + TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); - TEST_IMM_ZEROSRC1( 24, srli, 0, 32 ); - TEST_IMM_ZERODEST( 25, srli, 33, 50 ); + TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); + TEST_IMM_ZERODEST( 25, srli, 33, 10 ); TEST_PASSFAIL |