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| author | Andrew Waterman <andrew@sifive.com> | 2017-01-04 11:45:18 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-01-04 11:45:18 -0800 |
| commit | 6a1a38d421fd3e24bdc179d58d33572636b903b2 (patch) | |
| tree | d093b9b4450520b89860b5b86941f6b5f72df7e4 /isa | |
| parent | acc35f32c788fdcbb854f8fb6d74026050ced273 (diff) | |
| download | riscv-tests-6a1a38d421fd3e24bdc179d58d33572636b903b2.zip riscv-tests-6a1a38d421fd3e24bdc179d58d33572636b903b2.tar.gz riscv-tests-6a1a38d421fd3e24bdc179d58d33572636b903b2.tar.bz2 | |
Specify Spike ISA explicitly
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index 1afa4d6..3ed1b60 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -43,10 +43,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) $< 2> $@ + $(RISCV_SIM) --isa=rv64gc $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=RV32 $< 2> $@ + $(RISCV_SIM) --isa=rv32gc $< 2> $@ define compile_template |