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authorAndrew Waterman <andrew@sifive.com>2017-11-09 19:25:22 -0800
committerAndrew Waterman <andrew@sifive.com>2017-11-09 19:26:45 -0800
commitd9b4071ea4a9a2fe84a51443250184f51e931ac2 (patch)
treebe5529c46a722dfa50a63c9480ae1e045990a418 /isa
parent652ec8c0c98bfc64bbc8d036d89c61066aebee91 (diff)
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Make rv64mi-p-ecall work when U-mode is not present
Diffstat (limited to 'isa')
-rw-r--r--isa/rv64si/scall.S18
1 files changed, 17 insertions, 1 deletions
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index cb97635..1f5e6b7 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -26,6 +26,23 @@ RVTEST_CODE_BEGIN
li TESTNUM, 2
+ # This is the expected trap code.
+ li t1, CAUSE_USER_ECALL
+
+#ifdef __MACHINE_MODE
+ # If running in M mode, use mstatus.MPP to check existence of U mode.
+ # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+ li t0, MSTATUS_MPP
+ csrc mstatus, t0
+ csrr t1, mstatus
+ and t0, t0, t1
+ beqz t0, 1f
+
+ # If U mode doesn't exist, mcause should indicate ECALL from M mode.
+ li t1, CAUSE_MACHINE_ECALL
+#endif
+
+1:
li t0, SSTATUS_SPP
csrc sstatus, t0
la t0, 1f
@@ -42,7 +59,6 @@ RVTEST_CODE_BEGIN
.align 2
.global stvec_handler
stvec_handler:
- li t1, CAUSE_USER_ECALL
csrr t0, scause
bne t0, t1, fail
j pass