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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:43:01 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:43:01 -0800 |
| commit | 7f5d59f657b25bdd5bebdc6c8875c8cd629dd330 (patch) | |
| tree | 502b94e629d80b0bbefd130adb8f2037abd8d05b /isa | |
| parent | 7dfc16ad687186faa57368a251489e56b72b6f91 (diff) | |
| download | riscv-tests-7f5d59f657b25bdd5bebdc6c8875c8cd629dd330.zip riscv-tests-7f5d59f657b25bdd5bebdc6c8875c8cd629dd330.tar.gz riscv-tests-7f5d59f657b25bdd5bebdc6c8875c8cd629dd330.tar.bz2 | |
Check mbadaddr in ma_addr test
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/ma_addr.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index be3572f..ba96606 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -22,6 +22,7 @@ RVTEST_CODE_BEGIN #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \ li TESTNUM, testnum; \ + addi t1, base, offset; \ insn x0, offset(base); \ j fail \ @@ -70,6 +71,9 @@ mtvec_handler: csrr t0, mcause bne t0, s1, fail + csrr t0, mbadaddr + bne t0, t1, fail + csrr t0, mepc addi t0, t0, 8 csrw mepc, t0 |