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| author | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2014-04-08 21:53:19 -0700 |
|---|---|---|
| committer | Stephen Twigg <sdtwigg@eecs.berkeley.edu> | 2014-04-08 21:53:19 -0700 |
| commit | 8f6e2420926471a7bd9a660305ab3d6a22f22dc9 (patch) | |
| tree | 358c60a4de4597b4002928dbbc2f9e9101b7213c /isa | |
| parent | 8a86a3e45d2ca91ea218b92d3e7a1b73d00872e7 (diff) | |
| download | riscv-tests-8f6e2420926471a7bd9a660305ab3d6a22f22dc9.zip riscv-tests-8f6e2420926471a7bd9a660305ab3d6a22f22dc9.tar.gz riscv-tests-8f6e2420926471a7bd9a660305ab3d6a22f22dc9.tar.bz2 | |
Adjust hwacha misaligned instruction test to ignore lower 2 bits in comparisons to account for impl differences.
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64sv/ma_vt_inst.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S index cd7762d..d772041 100644 --- a/isa/rv64sv/ma_vt_inst.S +++ b/isa/rv64sv/ma_vt_inst.S @@ -48,6 +48,8 @@ handler: # check badvaddr vxcptaux a3 la a4,vtcode1+2 + andi a3, a3, -4 # mask off lower bits so that may + andi a4, a4, -4 # ignore impl. specific behavior bne a3,a4,fail # make sure vector unit has cleared out |