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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-02-27 16:09:10 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-02-27 16:09:10 -0800 |
| commit | 241c14dc57c71e45e0b3b9c90141ecc3404ecd05 (patch) | |
| tree | 000e44d552e1d74cd2b60afd7c1e4da9790bb27b /isa | |
| parent | 3e400b04627aacf42cfc6bc05efce22f67bdd788 (diff) | |
| download | riscv-tests-241c14dc57c71e45e0b3b9c90141ecc3404ecd05.zip riscv-tests-241c14dc57c71e45e0b3b9c90141ecc3404ecd05.tar.gz riscv-tests-241c14dc57c71e45e0b3b9c90141ecc3404ecd05.tar.bz2 | |
add keepcfg test
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64uv/Makefrag | 2 | ||||
| -rw-r--r-- | isa/rv64uv/keepcfg.S | 83 |
2 files changed, 84 insertions, 1 deletions
diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag index 1a92560..978a32b 100644 --- a/isa/rv64uv/Makefrag +++ b/isa/rv64uv/Makefrag @@ -4,7 +4,7 @@ rv64uv_sc_tests = \ wakeup fence \ - vsetcfgi vsetcfg vsetvl \ + vsetcfgi vsetcfg vsetvl keepcfg \ vmvv vmsv \ vfmvv vfmsv \ utidx \ diff --git a/isa/rv64uv/keepcfg.S b/isa/rv64uv/keepcfg.S new file mode 100644 index 0000000..b507405 --- /dev/null +++ b/isa/rv64uv/keepcfg.S @@ -0,0 +1,83 @@ +#***************************************************************************** +# utidx.S +#----------------------------------------------------------------------------- +# +# Test utidx instruction in a vf block. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UV +RVTEST_CODE_BEGIN + + vsetcfg 2,0 + li s0,2048 + vsetvl s0,s0 + + lui a0,%hi(vtcode1) + vf %lo(vtcode1)(a0) + la a4,dest1 + vsd vx1,a4 + + vsetcfg 3,0 + li s1,2048 + vsetvl s1,s1 + + lui a0,%hi(vtcode2) + vf %lo(vtcode2)(a0) + la a4,dest2 + vsd vx1,a4 + + fence + + la a4,dest1 + li a1,1 +loop1: + ld a0,0(a4) + addi TESTNUM,a1,2 + bne a0,a1,fail + addi a4,a4,8 + addi a1,a1,1 + bne a1,s0,loop1 + + la a4,dest2 + li a1,1024 + li a2,1 +loop2: + ld a0,0(a4) + addi TESTNUM,a1,2 + bne a0,a1,fail + addi a4,a4,8 + addi a1,a1,1 + addi a2,a2,1 + bne a2,s1,loop2 + + j pass + +vtcode1: + utidx x1 + addi x1,x1,1 + stop + +vtcode2: + utidx x1 + addi x1,x1,1024 + stop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +dest1: + .skip 16384 + +dest2: + .skip 16384 + +RVTEST_DATA_END |