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| author | Andrew Waterman <andrew@sifive.com> | 2016-12-06 17:04:14 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-12-06 17:04:14 -0800 |
| commit | 56f46aa0f9688c87ce9ebd7658e19b884b018b6b (patch) | |
| tree | 516d33de0c78bab0968f8548f7223160d8bba6fb /isa/rv64ui/srli.S | |
| parent | b68b39031a730ecc155ed87fba2ed5f111d0ab07 (diff) | |
| download | riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.zip riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.tar.gz riscv-tests-56f46aa0f9688c87ce9ebd7658e19b884b018b6b.tar.bz2 | |
avoid non-standard predefined macros
Diffstat (limited to 'isa/rv64ui/srli.S')
| -rw-r--r-- | isa/rv64ui/srli.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64ui/srli.S b/isa/rv64ui/srli.S index eae2532..88ee8d2 100644 --- a/isa/rv64ui/srli.S +++ b/isa/rv64ui/srli.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN #------------------------------------------------------------- #define TEST_SRL(n, v, a) \ - TEST_IMM_OP(n, srli, ((v) & ((1 << (_RISCV_SZLONG-1) << 1) - 1)) >> (a), v, a) + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) TEST_SRL( 2, 0xffffffff80000000, 0 ); TEST_SRL( 3, 0xffffffff80000000, 1 ); |