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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-22 14:56:59 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-22 14:56:59 -0700 |
| commit | 81ad66f25ce4c15180e558696961bd8eaf967fea (patch) | |
| tree | d70676fb1d11a4a66a268f7860d3ef7d469987fe /isa/rv64ui/sll.S | |
| download | riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.zip riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.tar.gz riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.tar.bz2 | |
initial commit
Diffstat (limited to 'isa/rv64ui/sll.S')
| -rw-r--r-- | isa/rv64ui/sll.S | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S new file mode 100644 index 0000000..935da3d --- /dev/null +++ b/isa/rv64ui/sll.S @@ -0,0 +1,88 @@ +#***************************************************************************** +# sll.S +#----------------------------------------------------------------------------- +# +# Test sll instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six bits + + TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sll, 0 ); + TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |