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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-17 00:37:17 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-17 00:38:24 -0700 |
| commit | c8c14a5c4f29655465296fd8e3b2371c6899f604 (patch) | |
| tree | 61afce73d9c2754af9b24515b6fb158925ca4e6c /isa/rv64ua | |
| parent | ef84dc3a8d7a95f3324662f9fb167d24b9dc900a (diff) | |
| download | riscv-tests-c8c14a5c4f29655465296fd8e3b2371c6899f604.zip riscv-tests-c8c14a5c4f29655465296fd8e3b2371c6899f604.tar.gz riscv-tests-c8c14a5c4f29655465296fd8e3b2371c6899f604.tar.bz2 | |
Improve AMO tests
- avoid code duplication between RV32 and RV64 variants
- make LR/SC do something interesting on uniprocessors
- avoid requiring M extension
Diffstat (limited to 'isa/rv64ua')
| -rw-r--r-- | isa/rv64ua/amoxor_w.S | 16 | ||||
| -rw-r--r-- | isa/rv64ua/lrsc.S | 23 |
2 files changed, 20 insertions, 19 deletions
diff --git a/isa/rv64ua/amoxor_w.S b/isa/rv64ua/amoxor_w.S index 2b92323..1b305dd 100644 --- a/isa/rv64ua/amoxor_w.S +++ b/isa/rv64ua/amoxor_w.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN li a0, 0xffffffff80000000; \ li a1, 0xfffffffffffff800; \ la a3, amo_operand; \ - sd a0, 0(a3); \ + sw a0, 0(a3); \ nop; nop; nop; nop; \ nop; nop; nop; nop; \ nop; nop; nop; nop; \ @@ -28,24 +28,24 @@ RVTEST_CODE_BEGIN amoxor.w a4, a1, 0(a3); \ ) - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ + TEST_CASE(4, a4, 0x7ffff800, \ li a1, 0xc0000001; \ li a4, 16384; \ add a5, a3, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ add a5, a5, a4; \ - ld x0, 0(a5); \ + lw x0, 0(a5); \ amoxor.w a4, a1, 0(a3); \ ) - TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) TEST_PASSFAIL diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index 9422739..11eb7de 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -40,9 +40,12 @@ TEST_CASE( 3, a4, 1, \ sc.w a4, a1, (a0); \ ) -# have each core add its coreid to foo 1000 times +#define LOG_ITERATIONS 10 + +# have each core add its coreid+1 to foo 1024 times la a0, foo -li a1, 1000 +li a1, 1<<LOG_ITERATIONS +addi a2, a2, 1 1: lr.w a4, (a0) add a4, a4, a2 sc.w a4, a4, (a0) @@ -58,15 +61,13 @@ amoadd.w x0, a1, (a0) blt a1, a3, 1b fence -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ +# expected result is 512*ncores*(ncores+1) +TEST_CASE( 4, a0, 0, \ + lw a0, foo; \ + slli a1, a3, LOG_ITERATIONS-1; \ +1:sub a0, a0, a1; \ + addi a3, a3, -1; \ + bgez a3, 1b ) TEST_PASSFAIL |