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| author | Andrew Waterman <andrew@sifive.com> | 2022-06-08 16:39:15 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-06-08 16:39:15 -0700 |
| commit | c73e991add1df5767dfb7092a067df6aec88b56f (patch) | |
| tree | 83880e1ebd8ee2e9cc722468e388ccc33e74c164 /isa/rv64mi | |
| parent | 0f07eccaf2139b129b074800cbbcfadee3b45a7e (diff) | |
| parent | fb04a343df61c55849edc7734bc2a60d615fe49c (diff) | |
| download | riscv-tests-c73e991add1df5767dfb7092a067df6aec88b56f.zip riscv-tests-c73e991add1df5767dfb7092a067df6aec88b56f.tar.gz riscv-tests-c73e991add1df5767dfb7092a067df6aec88b56f.tar.bz2 | |
Merge pull request #395 from riscv-software-src/misaligned_store
Test misaligned stores
Diffstat (limited to 'isa/rv64mi')
| -rw-r--r-- | isa/rv64mi/Makefrag | 3 | ||||
| -rw-r--r-- | isa/rv64mi/ld-misaligned.S | 45 | ||||
| -rw-r--r-- | isa/rv64mi/lh-misaligned.S | 38 | ||||
| -rw-r--r-- | isa/rv64mi/lw-misaligned.S | 40 |
4 files changed, 126 insertions, 0 deletions
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag index 645622b..2f88249 100644 --- a/isa/rv64mi/Makefrag +++ b/isa/rv64mi/Makefrag @@ -12,5 +12,8 @@ rv64mi_sc_tests = \ ma_addr \ scall \ sbreak \ + ld-misaligned \ + lw-misaligned \ + lh-misaligned \ rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) diff --git a/isa/rv64mi/ld-misaligned.S b/isa/rv64mi/ld-misaligned.S new file mode 100644 index 0000000..fb210ad --- /dev/null +++ b/isa/rv64mi/ld-misaligned.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, ld, 0x0807060504030201, 0, tdat ); + TEST_LD_OP( 3, ld, 0x0908070605040302, 1, tdat ); + TEST_LD_OP( 4, ld, 0x0a09080706050403, 2, tdat ); + TEST_LD_OP( 5, ld, 0x0b0a090807060504, 3, tdat ); + TEST_LD_OP( 6, ld, 0x0c0b0a0908070605, 4, tdat ); + TEST_LD_OP( 7, ld, 0x0d0c0b0a09080706, 5, tdat ); + TEST_LD_OP( 8, ld, 0x0e0d0c0b0a090807, 6, tdat ); + TEST_LD_OP( 9, ld, 0x0f0e0d0c0b0a0908, 7, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 + .byte 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + +RVTEST_DATA_END diff --git a/isa/rv64mi/lh-misaligned.S b/isa/rv64mi/lh-misaligned.S new file mode 100644 index 0000000..c21551d --- /dev/null +++ b/isa/rv64mi/lh-misaligned.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lh-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, lh, 0x0201, 0, tdat ); + TEST_LD_OP( 3, lh, 0x0302, 1, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04 + +RVTEST_DATA_END diff --git a/isa/rv64mi/lw-misaligned.S b/isa/rv64mi/lw-misaligned.S new file mode 100644 index 0000000..3029085 --- /dev/null +++ b/isa/rv64mi/lw-misaligned.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, lw, 0x04030201, 0, tdat ); + TEST_LD_OP( 3, lw, 0x05040302, 1, tdat ); + TEST_LD_OP( 4, lw, 0x06050403, 2, tdat ); + TEST_LD_OP( 5, lw, 0x07060504, 3, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 + +RVTEST_DATA_END |