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authorAndrew Waterman <andrew@sifive.com>2022-06-08 16:39:15 -0700
committerGitHub <noreply@github.com>2022-06-08 16:39:15 -0700
commitc73e991add1df5767dfb7092a067df6aec88b56f (patch)
tree83880e1ebd8ee2e9cc722468e388ccc33e74c164 /isa/rv64mi/lh-misaligned.S
parent0f07eccaf2139b129b074800cbbcfadee3b45a7e (diff)
parentfb04a343df61c55849edc7734bc2a60d615fe49c (diff)
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Merge pull request #395 from riscv-software-src/misaligned_store
Test misaligned stores
Diffstat (limited to 'isa/rv64mi/lh-misaligned.S')
-rw-r--r--isa/rv64mi/lh-misaligned.S38
1 files changed, 38 insertions, 0 deletions
diff --git a/isa/rv64mi/lh-misaligned.S b/isa/rv64mi/lh-misaligned.S
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+++ b/isa/rv64mi/lh-misaligned.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lh-unaligned.S
+#-----------------------------------------------------------------------------
+#
+# Test that misaligned loads work or raise the correct exception
+# This test assumes the target is little-endian
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+ TEST_LD_OP( 2, lh, 0x0201, 0, tdat );
+ TEST_LD_OP( 3, lh, 0x0302, 1, tdat );
+
+2:
+ TEST_PASSFAIL
+
+ .align 2
+ .global mtvec_handler
+mtvec_handler:
+ MISALIGNED_LOAD_HANDLER
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+ .byte 0x01, 0x02, 0x03, 0x04
+
+RVTEST_DATA_END