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authorAndrew Waterman <waterman@cs.berkeley.edu>2016-07-11 17:51:33 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-07-11 17:51:33 -0700
commitd5fa5fa7c233a219d9b2c1b1d0fbcab9bba986c7 (patch)
treee34fdfe1c6c782bb13c0451da5c3c60e8894e641 /isa/rv32ua
parent089f4aae4836af1f3f530fbedc3a43a685eae0d1 (diff)
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Merge rv32ua tests into rv64ua
Diffstat (limited to 'isa/rv32ua')
-rw-r--r--isa/rv32ua/amoadd_w.S64
-rw-r--r--isa/rv32ua/amoand_w.S64
-rw-r--r--isa/rv32ua/amomax_w.S48
-rw-r--r--isa/rv32ua/amomaxu_w.S48
-rw-r--r--isa/rv32ua/amomin_w.S48
-rw-r--r--isa/rv32ua/amominu_w.S48
-rw-r--r--isa/rv32ua/amoor_w.S64
7 files changed, 21 insertions, 363 deletions
diff --git a/isa/rv32ua/amoadd_w.S b/isa/rv32ua/amoadd_w.S
index 975ae1d..df4560d 100644
--- a/isa/rv32ua/amoadd_w.S
+++ b/isa/rv32ua/amoadd_w.S
@@ -1,65 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amoadd_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x7ffff800, \
- li a1, 0x80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amoadd_w.S"
diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S
index 7c989c2..b824483 100644
--- a/isa/rv32ua/amoand_w.S
+++ b/isa/rv32ua/amoand_w.S
@@ -1,65 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amoand.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x80000000, \
- li a1, 0x80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amoand_w.S"
diff --git a/isa/rv32ua/amomax_w.S b/isa/rv32ua/amomax_w.S
index 698cf26..899d7d6 100644
--- a/isa/rv32ua/amomax_w.S
+++ b/isa/rv32ua/amomax_w.S
@@ -1,49 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 1; \
- sw x0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 1, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amomax_w.S"
diff --git a/isa/rv32ua/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S
index 27c4ddf..662f023 100644
--- a/isa/rv32ua/amomaxu_w.S
+++ b/isa/rv32ua/amomaxu_w.S
@@ -1,49 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amomaxu_w.S"
diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S
index a6a0947..cbd88e6 100644
--- a/isa/rv32ua/amomin_w.S
+++ b/isa/rv32ua/amomin_w.S
@@ -1,49 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amomin_w.S"
diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S
index ce06e1c..acb0d79 100644
--- a/isa/rv32ua/amominu_w.S
+++ b/isa/rv32ua/amominu_w.S
@@ -1,49 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amominu_w.S"
diff --git a/isa/rv32ua/amoor_w.S b/isa/rv32ua/amoor_w.S
index 0988c66..0a2a57d 100644
--- a/isa/rv32ua/amoor_w.S
+++ b/isa/rv32ua/amoor_w.S
@@ -1,65 +1,7 @@
# See LICENSE for license details.
-#*****************************************************************************
-# amoor.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.w instruction.
-#
-
#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffff800, \
- li a1, 1; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+#include "../rv64ua/amoor_w.S"