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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-01 21:02:15 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-05-01 21:02:15 -0700 |
| commit | be72d6bacf1a14b85b142092bc47e4bfe68b38fd (patch) | |
| tree | 7712ba4ecd29c4451deaf2e2c266ff39f2c6eccd /env | |
| parent | 24d2144a30a06bea49ffd3010d43b152a5b50580 (diff) | |
| download | riscv-tests-be72d6bacf1a14b85b142092bc47e4bfe68b38fd.zip riscv-tests-be72d6bacf1a14b85b142092bc47e4bfe68b38fd.tar.gz riscv-tests-be72d6bacf1a14b85b142092bc47e4bfe68b38fd.tar.bz2 | |
pass all FP tests if FPU not present
Diffstat (limited to 'env')
| -rw-r--r-- | env/p/riscv_test.h | 6 | ||||
| -rw-r--r-- | env/pm/riscv_test.h | 6 | ||||
| -rw-r--r-- | env/pt/riscv_test.h | 6 | ||||
| -rw-r--r-- | env/v/riscv_test.h | 4 | ||||
| -rw-r--r-- | env/v/vm.c | 13 |
5 files changed, 17 insertions, 18 deletions
diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h index 35154f0..8ce8490 100644 --- a/env/p/riscv_test.h +++ b/env/p/riscv_test.h @@ -16,9 +16,9 @@ setpcr cr0, 2; \ mfpcr a0, cr0; \ and a0, a0, 2; \ - beqz a0, 1f; \ - mtfsr x0; \ -1: + bnez a0, 2f; \ + RVTEST_PASS; \ +2:mtfsr x0; \ #define RVTEST_VEC_ENABLE \ mfpcr a0, cr0; \ diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h index 357fd3d..fd07ead 100644 --- a/env/pm/riscv_test.h +++ b/env/pm/riscv_test.h @@ -13,9 +13,9 @@ setpcr cr0, 2; \ mfpcr a0, cr0; \ and a0, a0, 2; \ - beqz a0, 1f; \ - mtfsr x0; \ -1: + bnez a0, 2f; \ + RVTEST_PASS; \ +2:mtfsr x0; \ #define RVTEST_VEC_ENABLE \ mfpcr a0, cr0; \ diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h index 52f5f59..363e6e1 100644 --- a/env/pt/riscv_test.h +++ b/env/pt/riscv_test.h @@ -13,9 +13,9 @@ setpcr cr0, 2; \ mfpcr a0, cr0; \ and a0, a0, 2; \ - beqz a0, 1f; \ - mtfsr x0; \ -1: + bnez a0, 2f; \ + RVTEST_PASS; \ +2:mtfsr x0; \ #define RVTEST_VEC_ENABLE \ mfpcr a0, cr0; \ diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h index e37ec05..2a1710d 100644 --- a/env/v/riscv_test.h +++ b/env/v/riscv_test.h @@ -10,9 +10,6 @@ #define RVTEST_RV64S \ #define RVTEST_FP_ENABLE \ - mfpcr t0, cr0; \ - or t0, t0, 2; \ - mtpcr t0, cr0; \ mtfsr x0; \ #define RVTEST_VEC_ENABLE \ @@ -27,6 +24,7 @@ .align 13; \ .global userstart; \ userstart: \ + RVTEST_FP_ENABLE; \ //----------------------------------------------------------------------- // End Macro @@ -22,6 +22,7 @@ static void cputstring(const char* s) static void terminate(int code) { while (mtpcr(PCR_TOHOST, code)); + while (1); } #define stringify1(x) #x @@ -30,7 +31,6 @@ static void terminate(int code) if (x) break; \ cputstring("Assertion failed: " stringify(x)); \ terminate(3); \ - while(1); \ } while(0) #define RELOC(x) ((typeof(x))((char*)(x) + (PGSIZE*MAX_TEST_PAGES))) @@ -181,13 +181,17 @@ void handle_trap(trapframe_t* tf) evict(i*PGSIZE); terminate(n); - while(1); } else if (tf->cause == CAUSE_FAULT_FETCH) handle_fault(tf->epc); else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) { - if ((tf->insn & 0xF83FFFFF) == 0x37B) + int mtfsr; + asm ("la %0, 1f; lw %0, 0(%0); b 2f; 1: mtfsr x0; 2:" : "=r"(mtfsr)); + + if (tf->insn == mtfsr) + terminate(1); // FP test on non-FP hardware. "succeed." + else if ((tf->insn & 0xF83FFFFF) == 0x37B) emulate_vxcptsave(tf); else if ((tf->insn & 0xF83FFFFF) == 0x77B) emulate_vxcptrestore(tf); @@ -234,9 +238,6 @@ void vm_boot(long test_addr, long seed) mtpcr(PCR_PTBR, l1pt); mtpcr(PCR_SR, mfpcr(PCR_SR) | SR_VM | SR_EF); - if (mfpcr(PCR_SR) & SR_EF) - asm volatile ("mtfsr x0"); - // relocate long adjustment = RELOC(0L), tmp; mtpcr(PCR_EVEC, (char*)&trap_entry + adjustment); |