revamp hwacha tests

2 files changed, 17 insertions, 118 deletions

diff --git a/env/pt/pcr.h b/env/pt/pcr.h
deleted file mode 100644
index 72043b7..0000000
--- a/env/pt/pcr.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef _RISCV_PCR_H
-#define _RISCV_PCR_H
-
-#define SR_ET    0x00000001
-#define SR_EF    0x00000002
-#define SR_EV    0x00000004
-#define SR_EC    0x00000008
-#define SR_PS    0x00000010
-#define SR_S     0x00000020
-#define SR_U64   0x00000040
-#define SR_S64   0x00000080
-#define SR_VM    0x00000100
-#define SR_IM    0x00FF0000
-#define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
-#define SR_IM_SHIFT 16
-
-#define PCR_SR       0
-#define PCR_EPC      1
-#define PCR_BADVADDR 2
-#define PCR_EVEC     3
-#define PCR_COUNT    4
-#define PCR_COMPARE  5
-#define PCR_CAUSE    6
-#define PCR_PTBR     7
-#define PCR_SEND_IPI 8
-#define PCR_CLR_IPI  9
-#define PCR_COREID   10
-#define PCR_IMPL     11
-#define PCR_K0       12
-#define PCR_K1       13
-#define PCR_VECBANK  18
-#define PCR_VECCFG   19
-#define PCR_RESET    29
-#define PCR_TOHOST   30
-#define PCR_FROMHOST 31
-
-#define IMPL_ISASIM 1
-#define IMPL_ROCKET 2
-
-#define IRQ_IPI   5
-#define IRQ_TIMER 7
-
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_VECTOR_DISABLED 12
-#define CAUSE_VECTOR_BANK 13
-
-#define CAUSE_VECTOR_MISALIGNED_FETCH 24
-#define CAUSE_VECTOR_FAULT_FETCH 25
-#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
-#define CAUSE_VECTOR_ILLEGAL_COMMAND 27
-#define CAUSE_VECTOR_MISALIGNED_LOAD 28
-#define CAUSE_VECTOR_MISALIGNED_STORE 29
-#define CAUSE_VECTOR_FAULT_LOAD 30
-#define CAUSE_VECTOR_FAULT_STORE 31
-
-#ifdef __riscv
-
-#define ASM_CR(r)   _ASM_CR(r)
-#define _ASM_CR(r)  cr##r
-
-#ifndef __ASSEMBLER__
-
-#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
-          asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
-          __tmp2; })
-
-#define mfpcr(reg) ({ long __tmp; \
-          asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
-          __tmp; })
-
-#define setpcr(reg,val) ({ long __tmp; \
-          asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
-          __tmp; })
-
-#define clearpcr(reg,val) ({ long __tmp; \
-          asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
-          __tmp; })
-
-#endif
-
-#endif
-
-#endif
diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h
index 822dcfa..e56267f 100644
--- a/env/pt/riscv_test.h
+++ b/env/pt/riscv_test.h
@@ -81,21 +81,20 @@ evac:                              \
 //-----------------------------------------------------------------------
 
 #define ENABLE_TIMER_INTERRUPT \
-        mtpcr x0,ASM_CR(PCR_CLR_IPI);\
-        mfpcr a0,ASM_CR(PCR_SR);     \
-        li a1, SR_ET|SR_IM;          \
-        or a0,a0,a1;                 \
-        mtpcr a0,ASM_CR(PCR_SR);     \
+        mtpcr x0,clear_ipi;          \
+        mfpcr a0,status;             \
+        li a1,SR_IM;                 \
+        mtpcr a0,status;             \
         la a0,_handler;              \
-        mtpcr a0,ASM_CR(PCR_EVEC);   \
-        mtpcr x0,ASM_CR(PCR_COUNT);  \
+        mtpcr a0,evec;               \
+        mtpcr x0,count;              \
         addi a0,x0,60;               \
-        mtpcr a0,ASM_CR(PCR_COMPARE);\
+        mtpcr a0,compare;            \
 
 #define XCPT_HANDLER \
 _handler: \
-        mtpcr a0,ASM_CR(PCR_K0);     \
-        mtpcr a1,ASM_CR(PCR_K1);     \
+        mtpcr a0,sup0;               \
+        mtpcr a1,sup1;               \
         la a0,regspill;              \
         sd a2,0(a0);                 \
         sd a3,8(a0);                 \
@@ -103,19 +102,12 @@ _handler: \
         sd a5,24(a0);                \
         sd s0,32(a0);                \
         sd s1,40(a0);                \
-        mfpcr s1,ASM_CR(PCR_VECBANK);\
-        mfpcr s0,ASM_CR(PCR_VECCFG); \
+        vgetcfg s0;                  \
+        vgetvl s1;                   \
         la a0,evac;                  \
         vxcptevac a0;                \
-        mtpcr s1,ASM_CR(PCR_VECBANK);\
-        srli a1,s0,12;               \
-        andi a1,a1,0x3f;             \
-        srli a2,s0,18;               \
-        andi a2,a2,0x3f;             \
-        vvcfg a1,a2;                 \
-        li a2,0xfff;                 \
-        and a1,s0,a2;                \
-        vsetvl a1,a1;                \
+        vsetcfg s0;                  \
+        vsetvl s1,s1;                \
         vxcpthold;                   \
         li a5,0;                     \
 _handler_loop: \
@@ -167,11 +159,11 @@ _done_skip: \
         ld a5,24(a0);                \
         ld s0,32(a0);                \
         ld s1,40(a0);                \
-        mfpcr a0,ASM_CR(PCR_COUNT);  \
+        mfpcr a0,count;              \
         addi a0,a0,60;               \
-        mtpcr a0,ASM_CR(PCR_COMPARE);\
-        mfpcr a0,ASM_CR(PCR_K0);     \
-        mfpcr a1,ASM_CR(PCR_K1);     \
+        mtpcr a0,compare;            \
+        mfpcr a0,sup0;               \
+        mfpcr a1,sup1;               \
         eret;                        \
 
 #endif