aboutsummaryrefslogtreecommitdiff
path: root/debug
diff options
context:
space:
mode:
authorTim Newsome <tim@sifive.com>2017-12-01 14:29:11 -0800
committerTim Newsome <tim@sifive.com>2017-12-01 14:29:11 -0800
commitb747a10a7dd789620ebcde2197581ef8bf0fda33 (patch)
treeaff2d7f69d1df798c28509bd62509281b10f2b74 /debug
parentfda427b8110777add52890641c49155f363d39ae (diff)
downloadriscv-tests-b747a10a7dd789620ebcde2197581ef8bf0fda33.zip
riscv-tests-b747a10a7dd789620ebcde2197581ef8bf0fda33.tar.gz
riscv-tests-b747a10a7dd789620ebcde2197581ef8bf0fda33.tar.bz2
Ensure there are no unnamed registers.
Diffstat (limited to 'debug')
-rwxr-xr-xdebug/gdbserver.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 49e42e7..521fffb 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -396,6 +396,8 @@ class Registers(DebugTest):
output = self.gdb.command(cmd)
for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
assertIn(reg, output)
+ for line in output.splitlines():
+ assertRegexpMatches(line, r"^\S")
#TODO
# mcpuid is one of the few registers that should have the high bit set