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| author | Megan Wachs <megan@sifive.com> | 2016-08-08 12:24:44 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2016-08-08 12:24:44 -0700 |
| commit | b00a402f5d921fda37a7e5e59b8d4c566467f0a4 (patch) | |
| tree | d0ecf349ae581c2ee593a86e5c25fae37948fcd3 /debug | |
| parent | 57a2595e46680771d8341e68679592c291ea024c (diff) | |
| download | riscv-tests-b00a402f5d921fda37a7e5e59b8d4c566467f0a4.zip riscv-tests-b00a402f5d921fda37a7e5e59b8d4c566467f0a4.tar.gz riscv-tests-b00a402f5d921fda37a7e5e59b8d4c566467f0a4.tar.bz2 | |
By default debug=False
Diffstat (limited to 'debug')
| -rwxr-xr-x | debug/gdbserver.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 0693518..9d6f781 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -593,7 +593,7 @@ class FreedomE300SimTarget(Target): instruction_hardware_breakpoint_count = 2 def server(self): - sim = testlib.VcsSim(simv=parsed.run, debug=True) + sim = testlib.VcsSim(simv=parsed.run, debug=False) x = testlib.Openocd(cmd=parsed.cmd, config="targets/%s/openocd.cfg" % self.name, otherProcess = sim) @@ -610,7 +610,7 @@ class FreedomU500SimTarget(Target): instruction_hardware_breakpoint_count = 2 def server(self): - sim = testlib.VcsSim(simv=parsed.run, debug=True) + sim = testlib.VcsSim(simv=parsed.run, debug=False) x = testlib.Openocd(cmd=parsed.cmd, config="targets/%s/openocd.cfg" % self.name, otherProcess = sim) |