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authorTim Newsome <tim@sifive.com>2019-05-16 14:39:28 -0700
committerGitHub <noreply@github.com>2019-05-16 14:39:28 -0700
commitb7a0a80210c77c1d817243963ce35fba3ec97851 (patch)
treebaa8d87e2f8ef6c62948b061856fcaf7347515d1 /debug
parentfbf5f3a2589c61d34569524dbf353beda0b6b4de (diff)
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Cover with/without halt groups. (#191)
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
Diffstat (limited to 'debug')
-rw-r--r--debug/targets/RISC-V/spike32-2-hwthread.py4
-rw-r--r--debug/targets/RISC-V/spike32-2-rtos.py3
-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike32.py2
-rw-r--r--debug/testlib.py21
5 files changed, 20 insertions, 12 deletions
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py
index 333a7f2..c5fe92d 100644
--- a/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -8,7 +8,7 @@ class spike32_2(targets.Target):
openocd_config_path = "spike-2-hwthread.cfg"
timeout_sec = 5
implements_custom_test = True
- support_hasel = False
def create(self):
- return testlib.Spike(self, support_hasel=False)
+ return testlib.Spike(self, support_hasel=True,
+ support_haltgroups=False)
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index 3a2e8b8..335a3d7 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -12,4 +12,5 @@ class spike32_2(targets.Target):
def create(self):
return testlib.Spike(self, progbufsize=0, dmi_rti=4,
- support_hasel=False, support_abstract_csr=True)
+ support_hasel=False, support_abstract_csr=True,
+ support_haltgroups=False)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index a6fac39..6203214 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -11,4 +11,4 @@ class spike32_2(targets.Target):
def create(self):
return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4,
- support_abstract_csr=True)
+ support_abstract_csr=True, support_haltgroups=False)
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 6894bcf..e8726b9 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -18,4 +18,4 @@ class spike32(targets.Target):
def create(self):
# 64-bit FPRs on 32-bit target
return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4,
- support_abstract_csr=True)
+ support_abstract_csr=True, support_haltgroups=False)
diff --git a/debug/testlib.py b/debug/testlib.py
index d0383cb..960f444 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -57,9 +57,11 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
class Spike(object):
# pylint: disable=too-many-instance-attributes
+ # pylint: disable=too-many-locals
def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
- support_hasel=True, support_abstract_csr=True):
+ support_hasel=True, support_abstract_csr=True,
+ support_haltgroups=True):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
@@ -69,6 +71,7 @@ class Spike(object):
self.abstract_rti = abstract_rti
self.support_abstract_csr = support_abstract_csr
self.support_hasel = support_hasel
+ self.support_haltgroups = support_haltgroups
if target.harts:
harts = target.harts
@@ -105,6 +108,7 @@ class Spike(object):
raise Exception("Didn't get spike message about bitbang "
"connection")
+ # pylint: disable=too-many-branches
def command(self, target, harts, halted, timeout, with_jtag_gdb):
# pylint: disable=no-self-use
if target.sim_cmd:
@@ -124,23 +128,26 @@ class Spike(object):
isa = "RV%dG" % harts[0].xlen
cmd += ["--isa", isa]
- cmd += ["--debug-auth"]
+ cmd += ["--dm-auth"]
if not self.progbufsize is None:
- cmd += ["--progsize", str(self.progbufsize)]
- cmd += ["--debug-sba", "32"]
+ cmd += ["--dm-progsize", str(self.progbufsize)]
+ cmd += ["--dm-sba", "32"]
if not self.dmi_rti is None:
cmd += ["--dmi-rti", str(self.dmi_rti)]
if not self.abstract_rti is None:
- cmd += ["--abstract-rti", str(self.abstract_rti)]
+ cmd += ["--dm-abstract-rti", str(self.abstract_rti)]
if not self.support_abstract_csr:
- cmd.append("--debug-no-abstract-csr")
+ cmd.append("--dm-no-abstract-csr")
if not self.support_hasel:
- cmd.append("--without-hasel")
+ cmd.append("--dm-no-hasel")
+
+ if not self.support_haltgroups:
+ cmd.append("--dm-no-halt-groups")
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"