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| author | Richard Xia <richardxia@richardxia.com> | 2017-10-30 15:44:21 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-10-30 15:44:21 -0700 |
| commit | 4a6eddab8ec709180e6294ce3794768a511baf82 (patch) | |
| tree | 542ad51135fab58f607d83aff1c119231b7e8590 /debug | |
| parent | dc87148473bc407d91ab8b4a6e69f7eade79bfa0 (diff) | |
| download | riscv-tests-4a6eddab8ec709180e6294ce3794768a511baf82.zip riscv-tests-4a6eddab8ec709180e6294ce3794768a511baf82.tar.gz riscv-tests-4a6eddab8ec709180e6294ce3794768a511baf82.tar.bz2 | |
Remove cache miss test from last AMO test. (#88)
Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07.
The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.
Diffstat (limited to 'debug')
0 files changed, 0 insertions, 0 deletions