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| author | Tim Newsome <tim@sifive.com> | 2018-02-27 14:28:26 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-02-27 14:28:26 -0800 |
| commit | db31c3dd894bca1e7aed903a159cf0e794f177c0 (patch) | |
| tree | a5c7cade840b119882b46e42b4dd6bed752f91b9 /debug/testlib.py | |
| parent | ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241 (diff) | |
| download | riscv-tests-db31c3dd894bca1e7aed903a159cf0e794f177c0.zip riscv-tests-db31c3dd894bca1e7aed903a159cf0e794f177c0.tar.gz riscv-tests-db31c3dd894bca1e7aed903a159cf0e794f177c0.tar.bz2 | |
Test debug authentication.debug_auth
Also halt instead of reset spike targets, which tests a more complicated
code path.
Diffstat (limited to 'debug/testlib.py')
| -rw-r--r-- | debug/testlib.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index 3aaa542..735dcba 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -117,6 +117,7 @@ class Spike(object): isa = "RV%dG" % harts[0].xlen cmd += ["--isa", isa] + cmd += ["--debug-auth"] assert len(set(t.ram for t in harts)) == 1, \ "All spike harts must have the same RAM layout" |