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| author | Tim Newsome <tim@sifive.com> | 2019-04-08 10:59:55 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-08 10:59:55 -0700 |
| commit | d8177046a0809eb29241641c040eff81ead8a8de (patch) | |
| tree | 71b9a53e6be40772891e35560440ba169210b175 /debug/targets | |
| parent | 74aecdcce266d2d7f73df415cb83b6e7816e0dc5 (diff) | |
| download | riscv-tests-d8177046a0809eb29241641c040eff81ead8a8de.zip riscv-tests-d8177046a0809eb29241641c040eff81ead8a8de.tar.gz riscv-tests-d8177046a0809eb29241641c040eff81ead8a8de.tar.bz2 | |
Test lack of abstract CSR access. (#187)
Diffstat (limited to 'debug/targets')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2-rtos.py | 3 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 2 |
6 files changed, 9 insertions, 6 deletions
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index 4b29801..3a2e8b8 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -12,4 +12,4 @@ class spike32_2(targets.Target): def create(self): return testlib.Spike(self, progbufsize=0, dmi_rti=4, - support_hasel=False) + support_hasel=False, support_abstract_csr=True) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 8872ad3..a6fac39 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -10,4 +10,5 @@ class spike32_2(targets.Target): implements_custom_test = True def create(self): - return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4) + return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4, + support_abstract_csr=True) diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index e633eea..6894bcf 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -17,4 +17,5 @@ class spike32(targets.Target): def create(self): # 64-bit FPRs on 32-bit target - return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4) + return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4, + support_abstract_csr=True) diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 3e7c221..8dee51a 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -11,4 +11,5 @@ class spike64_2_rtos(targets.Target): support_hasel = False def create(self): - return testlib.Spike(self, abstract_rti=30, support_hasel=False) + return testlib.Spike(self, abstract_rti=30, support_hasel=False, + support_abstract_csr=False) diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index beccae3..596098d 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -12,4 +12,4 @@ class spike64_2(targets.Target): def create(self): return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30, - support_hasel=False) + support_hasel=False, support_abstract_csr=False) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index fdb1282..c4c7796 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -18,4 +18,4 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0, - abstract_rti=30) + abstract_rti=30, support_abstract_csr=True) |