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authorTim Newsome <tim@sifive.com>2017-10-24 11:55:01 -0700
committerTim Newsome <tim@sifive.com>2017-10-24 11:55:01 -0700
commit3d284202d1440fe7aa029fa667aec9d45b4c4892 (patch)
tree85c70ec786712cbba34b0b6aa429bfab753acbb1 /debug/targets/RISC-V
parent4e240fc239ea96243c15d21f69d46493c2802a40 (diff)
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Increase dual-core RV64 timeouts.
I need this for CompareSections to pass when I instrument spike to be really slow.
Diffstat (limited to 'debug/targets/RISC-V')
-rw-r--r--debug/targets/RISC-V/spike64-2-rtos.py2
-rw-r--r--debug/targets/RISC-V/spike64-2.py2
2 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index d65d2ab..7e3fc7e 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -6,7 +6,7 @@ import spike64 # pylint: disable=import-error
class spike64_2_rtos(targets.Target):
harts = [spike64.spike64_hart(), spike64.spike64_hart()]
openocd_config_path = "spike-rtos.cfg"
- timeout_sec = 30
+ timeout_sec = 60
def create(self):
return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 709ebbe..79aab3e 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -6,7 +6,7 @@ import spike64 # pylint: disable=import-error
class spike64_2(targets.Target):
harts = [spike64.spike64_hart(), spike64.spike64_hart()]
openocd_config_path = "spike-2.cfg"
- timeout_sec = 30
+ timeout_sec = 60
def create(self):
return testlib.Spike(self)