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| author | Tim Newsome <tim@sifive.com> | 2020-02-14 14:54:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-14 14:54:07 -0800 |
| commit | 10706c544e9bca0cf2dc3867c9d3dbb77c53fa3b (patch) | |
| tree | ae4fb72db6a88e89f8634de170b194f187c551cd /debug/targets/RISC-V/spike64-2.py | |
| parent | abfa60c8c94d40d726d2f4bd03222ac8cff585aa (diff) | |
| download | riscv-tests-10706c544e9bca0cf2dc3867c9d3dbb77c53fa3b.zip riscv-tests-10706c544e9bca0cf2dc3867c9d3dbb77c53fa3b.tar.gz riscv-tests-10706c544e9bca0cf2dc3867c9d3dbb77c53fa3b.tar.bz2 | |
Add tests for vector register access (#244)
* WIP
* Add vector register smoketest.
Also redo the gdb value parsing code to accommodate the more complicated
way that vector registers look.
* Test vector access a little more thoroughly.
* Revert unnecessary changes.
Diffstat (limited to 'debug/targets/RISC-V/spike64-2.py')
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 6b9b5c9..5ace23b 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -4,8 +4,8 @@ import testlib import spike64 # pylint: disable=import-error class spike64_2(targets.Target): - harts = [spike64.spike64_hart(misa=0x8000000000141129), - spike64.spike64_hart(misa=0x8000000000141129)] + harts = [spike64.spike64_hart(misa=0x8000000000341129), + spike64.spike64_hart(misa=0x8000000000341129)] openocd_config_path = "spike-2.cfg" # Increased timeout because we use abstract_rti to artificially slow things # down. @@ -14,5 +14,6 @@ class spike64_2(targets.Target): support_hasel = False def create(self): - return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30, - support_hasel=False, support_abstract_csr=False) + return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, + support_hasel=False, support_abstract_csr=False, + vlen=512, elen=64) |