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| author | Tim Newsome <tim@sifive.com> | 2017-10-04 12:40:30 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-04 12:40:30 -0700 |
| commit | bf90ee0cf31a7cd0b2c535592f9970a300a8f1a5 (patch) | |
| tree | cb9b8c17d6b6366ec287097a13b36d954da61d2c /debug/targets/RISC-V/spike-2.cfg | |
| parent | 76029e5a96545c6cc97bce17b69f99dcb51c5f6c (diff) | |
| parent | 49fc83aa23045abee5d396ef5a9d96b80c03178d (diff) | |
| download | riscv-tests-bf90ee0cf31a7cd0b2c535592f9970a300a8f1a5.zip riscv-tests-bf90ee0cf31a7cd0b2c535592f9970a300a8f1a5.tar.gz riscv-tests-bf90ee0cf31a7cd0b2c535592f9970a300a8f1a5.tar.bz2 | |
Merge pull request #79 from riscv/multigdb
Multigdb support
Diffstat (limited to 'debug/targets/RISC-V/spike-2.cfg')
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg new file mode 100644 index 0000000..17526ec --- /dev/null +++ b/debug/targets/RISC-V/spike-2.cfg @@ -0,0 +1,19 @@ +# Connect to a mult-icore RISC-V target, exposing each hart as a thread. +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME_0 $_CHIPNAME.cpu0 +set _TARGETNAME_1 $_CHIPNAME.cpu1 +target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 +target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 + +gdb_report_data_abort enable + +init +reset halt |