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| author | Tim Newsome <tim@sifive.com> | 2017-02-21 13:07:14 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-21 13:07:14 -0800 |
| commit | f6eb7e9f880cb153bd4001d062f493886c0c5c06 (patch) | |
| tree | a333ead6d946263b5033737bab734bb4342939f5 /debug/targets.py | |
| parent | 7dfc16ad687186faa57368a251489e56b72b6f91 (diff) | |
| download | riscv-tests-f6eb7e9f880cb153bd4001d062f493886c0c5c06.zip riscv-tests-f6eb7e9f880cb153bd4001d062f493886c0c5c06.tar.gz riscv-tests-f6eb7e9f880cb153bd4001d062f493886c0c5c06.tar.bz2 | |
Talk to spike using OpenOCD instead of directly.
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index 52b623c..5ac62a8 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -68,20 +68,21 @@ class SpikeTarget(Target): ram_size = 5 * 1024 * 1024 instruction_hardware_breakpoint_count = 4 reset_vector = 0x1000 + openocd_config = "targets/%s/openocd.cfg" % directory class Spike64Target(SpikeTarget): name = "spike64" xlen = 64 use_fpu = True - def server(self): + def target(self): return testlib.Spike(self.cmd, halted=True) class Spike32Target(SpikeTarget): name = "spike32" xlen = 32 - def server(self): + def target(self): return testlib.Spike(self.cmd, halted=True, xlen=32) class FreedomE300Target(Target): |