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| author | Tim Newsome <tim@sifive.com> | 2017-08-10 11:43:49 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-08-10 11:43:49 -0700 |
| commit | d44ebb21c0131c661575539771a1d97fc9afa4c1 (patch) | |
| tree | 2c0b0ee2210e50b061a9e06f1fc8383fb7e33b79 /debug/pylint.rc | |
| parent | 130702297a010b4a2e7452bb48f0da88c0b30aa9 (diff) | |
| download | riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.zip riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.tar.gz riscv-tests-d44ebb21c0131c661575539771a1d97fc9afa4c1.tar.bz2 | |
Give these sim targets a chance of passing.
Also make sure vsim.log makes it into the generated log file.
Diffstat (limited to 'debug/pylint.rc')
0 files changed, 0 insertions, 0 deletions