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| author | Tim Newsome <tim@sifive.com> | 2017-07-31 13:49:34 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-07-31 13:49:34 -0700 |
| commit | ea9e37ff1411a8648710b5539b0971bb5ae9571f (patch) | |
| tree | 272c3236d5a03123ff705a914f16bdb81805ea12 /debug/programs | |
| parent | ccdbc82219827853a4152ff37fc1eab6602bf83e (diff) | |
| download | riscv-tests-ea9e37ff1411a8648710b5539b0971bb5ae9571f.zip riscv-tests-ea9e37ff1411a8648710b5539b0971bb5ae9571f.tar.gz riscv-tests-ea9e37ff1411a8648710b5539b0971bb5ae9571f.tar.bz2 | |
Fix the end of MulticoreTest.
Now it actually confirms that we're talking to two different cores which
have different values in their registers. Previously it could have been
fooled if eg. the thread command was a nop.
Diffstat (limited to 'debug/programs')
0 files changed, 0 insertions, 0 deletions