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| author | Tim Newsome <tim@sifive.com> | 2017-07-20 20:43:18 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-07-20 20:43:18 -0700 |
| commit | e9de1c77dda6c191cf871d1ad2b43448e83077b7 (patch) | |
| tree | b4d9817c7d539a69d1ac765eb6781a42f25d713e /debug/programs | |
| parent | 8ec0e8c02d1b1db0112c8564888f2d8dd88cbe15 (diff) | |
| download | riscv-tests-e9de1c77dda6c191cf871d1ad2b43448e83077b7.zip riscv-tests-e9de1c77dda6c191cf871d1ad2b43448e83077b7.tar.gz riscv-tests-e9de1c77dda6c191cf871d1ad2b43448e83077b7.tar.bz2 | |
Add back code to clean up triggers in entry.S
Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 302d409..ff8ae30 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -64,6 +64,15 @@ handle_reset: # initialize stack pointer la sp, stack_top + # Clear all hardware triggers + li t0, ~0 +1: + addi t0, t0, 1 + csrw CSR_TSELECT, t0 + csrw CSR_TDATA1, zero + csrr t1, CSR_TSELECT + beq t0, t1, 1b + # perform the rest of initialization in C j _init |