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| author | Tim Newsome <tim@sifive.com> | 2016-07-28 14:47:12 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-28 14:47:12 -0700 |
| commit | 7b3fcbe9a9d336b67b914b842ff656aaafe7d939 (patch) | |
| tree | 428b8fc69f3004d225e595bb8d991f99667ce292 /debug/programs | |
| parent | 553f2a265fe62b514cb97fdbd80ea1743de6e3cf (diff) | |
| download | riscv-tests-7b3fcbe9a9d336b67b914b842ff656aaafe7d939.zip riscv-tests-7b3fcbe9a9d336b67b914b842ff656aaafe7d939.tar.gz riscv-tests-7b3fcbe9a9d336b67b914b842ff656aaafe7d939.tar.bz2 | |
Add tests for virtual priv register.
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
Diffstat (limited to 'debug/programs')
| -rw-r--r-- | debug/programs/priv.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/debug/programs/priv.S b/debug/programs/priv.S new file mode 100644 index 0000000..2d20a65 --- /dev/null +++ b/debug/programs/priv.S @@ -0,0 +1,11 @@ +#include "../../env/encoding.h" + + .global main + + .section .text +main: + # MISA is only readable from machine mode + csrr t0, CSR_MISA + csrr t0, CSR_MISA + csrr t0, CSR_MISA + csrr t0, CSR_MISA |