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| author | Tim Newsome <tim@sifive.com> | 2016-06-10 10:45:27 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-18 18:51:54 -0700 |
| commit | 6ccc0bdde5eea898e88961f49e755bd2b4577792 (patch) | |
| tree | 20320df9cab3b239c310f589b6c38364c32f1df3 /debug/programs | |
| parent | 2088d1bce6558a101c42861dc578f4c7d7f4f6b4 (diff) | |
| download | riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.zip riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.tar.gz riscv-tests-6ccc0bdde5eea898e88961f49e755bd2b4577792.tar.bz2 | |
Add simple register tests.
Make the RegsTest case a bit more comprehensible.
Diffstat (limited to 'debug/programs')
| -rw-r--r-- | debug/programs/regs.S | 61 |
1 files changed, 31 insertions, 30 deletions
diff --git a/debug/programs/regs.S b/debug/programs/regs.S index 989d037..2cacd4f 100644 --- a/debug/programs/regs.S +++ b/debug/programs/regs.S @@ -12,39 +12,40 @@ .global main main: + nop j main write_regs: - SREG x1, 0(a0) - SREG x2, 8(a0) - SREG x3, 16(a0) - SREG x4, 24(a0) - SREG x5, 32(a0) - SREG x6, 40(a0) - SREG x7, 48(a0) - SREG x8, 56(a0) - SREG x9, 64(a0) - SREG x11, 72(a0) - SREG x12, 80(a0) - SREG x13, 88(a0) - SREG x14, 96(a0) - SREG x15, 104(a0) - SREG x16, 112(a0) - SREG x17, 120(a0) - SREG x18, 128(a0) - SREG x19, 136(a0) - SREG x20, 144(a0) - SREG x21, 152(a0) - SREG x22, 160(a0) - SREG x23, 168(a0) - SREG x24, 176(a0) - SREG x25, 184(a0) - SREG x26, 192(a0) - SREG x27, 200(a0) - SREG x28, 208(a0) - SREG x29, 216(a0) - SREG x30, 224(a0) - SREG x31, 232(a0) + SREG x2, 0(x1) + SREG x3, 8(x1) + SREG x4, 16(x1) + SREG x5, 24(x1) + SREG x6, 32(x1) + SREG x7, 40(x1) + SREG x8, 48(x1) + SREG x9, 56(x1) + SREG x10, 64(x1) + SREG x11, 72(x1) + SREG x12, 80(x1) + SREG x13, 88(x1) + SREG x14, 96(x1) + SREG x15, 104(x1) + SREG x16, 112(x1) + SREG x17, 120(x1) + SREG x18, 128(x1) + SREG x19, 136(x1) + SREG x20, 144(x1) + SREG x21, 152(x1) + SREG x22, 160(x1) + SREG x23, 168(x1) + SREG x24, 176(x1) + SREG x25, 184(x1) + SREG x26, 192(x1) + SREG x27, 200(x1) + SREG x28, 208(x1) + SREG x29, 216(x1) + SREG x30, 224(x1) + SREG x31, 232(x1) csrr x1, CSR_MSCRATCH |