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| author | Tim Newsome <tim@sifive.com> | 2016-07-18 18:33:10 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-07-19 11:24:25 -0700 |
| commit | 519794c8e91d1362dca8add5077277cc9bdc1611 (patch) | |
| tree | ab4f41d21775421cf66242b1bd487b4e291578fb /debug/programs | |
| parent | 713f6a3089ac8b656d0a18874782e26d3039b22e (diff) | |
| download | riscv-tests-519794c8e91d1362dca8add5077277cc9bdc1611.zip riscv-tests-519794c8e91d1362dca8add5077277cc9bdc1611.tar.gz riscv-tests-519794c8e91d1362dca8add5077277cc9bdc1611.tar.bz2 | |
Add 32-bit support.
Diffstat (limited to 'debug/programs')
| -rw-r--r-- | debug/programs/mprv.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S index 2725b67..115ccb5 100644 --- a/debug/programs/mprv.S +++ b/debug/programs/mprv.S @@ -12,7 +12,11 @@ main: # update mstatus csrr t1, CSR_MSTATUS +#ifdef __riscv32 + li t0, (MSTATUS_MPRV | (VM_SV32 << 24)) +#else li t0, (MSTATUS_MPRV | (VM_SV39 << 24)) +#endif #li t0, ((VM_SV39 << 24)) or t1, t0, t1 csrw CSR_MSTATUS, t1 @@ -34,5 +38,9 @@ data: .balign 0x1000 page_table: - .word ((0x80000000 >> 2) | PTE_V | PTE_TYPE_URWX_SRWX) +#ifdef __riscv32 + .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) +#else + .word ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U) .word 0 +#endif |