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| author | Tim Newsome <tim@sifive.com> | 2019-07-15 10:31:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-15 10:31:23 -0700 |
| commit | 419dcecc7a9eb0b8efc2e8c82d37364a724e2227 (patch) | |
| tree | 04854a0e0f6381cd4dbdb20e63a297265be77e3f /debug/programs | |
| parent | 92862bcb27a53f246126c95203b44153d324bbd7 (diff) | |
| download | riscv-tests-419dcecc7a9eb0b8efc2e8c82d37364a724e2227.zip riscv-tests-419dcecc7a9eb0b8efc2e8c82d37364a724e2227.tar.gz riscv-tests-419dcecc7a9eb0b8efc2e8c82d37364a724e2227.tar.bz2 | |
Make tests work with RV32E targets. (#196)
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 15 | ||||
| -rw-r--r-- | debug/programs/regs.S | 2 |
2 files changed, 13 insertions, 4 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 3acd786..3796b3b 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -59,14 +59,17 @@ handle_reset: .option pop # Initialize stack pointer. + la sp, stack_bottom # Give each hart STACK_SIZE of stack. # Assume hart IDs are contiguous and start at 0. + li t1, STACK_SIZE csrr t0, CSR_MHARTID + # Don't use mul instruction because not all harts support it. addi t0, t0, 1 - li t1, STACK_SIZE - mul t0, t0, t1 - la sp, stack_bottom - add sp, sp, t0 +1: + add sp, sp, t1 + addi t0, t0, -1 + bnez t0, 1b # Clear all hardware triggers li t0, ~0 @@ -125,6 +128,7 @@ trap_entry: SREG x13, 13*REGBYTES(sp) SREG x14, 14*REGBYTES(sp) SREG x15, 15*REGBYTES(sp) +#ifndef RV32E SREG x16, 16*REGBYTES(sp) SREG x17, 17*REGBYTES(sp) SREG x18, 18*REGBYTES(sp) @@ -141,6 +145,7 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) +#endif csrr a0, mcause csrr a1, mepc @@ -167,6 +172,7 @@ trap_entry: LREG x13, 13*REGBYTES(sp) LREG x14, 14*REGBYTES(sp) LREG x15, 15*REGBYTES(sp) +#ifndef RV32E LREG x16, 16*REGBYTES(sp) LREG x17, 17*REGBYTES(sp) LREG x18, 18*REGBYTES(sp) @@ -183,6 +189,7 @@ trap_entry: LREG x29, 29*REGBYTES(sp) LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) +#endif addi sp, sp, 32*REGBYTES mret diff --git a/debug/programs/regs.S b/debug/programs/regs.S index 63889dc..cfa1179 100644 --- a/debug/programs/regs.S +++ b/debug/programs/regs.S @@ -30,6 +30,7 @@ write_regs: SREG x13, 88(x1) SREG x14, 96(x1) SREG x15, 104(x1) +#ifndef RV32E SREG x16, 112(x1) SREG x17, 120(x1) SREG x18, 128(x1) @@ -46,6 +47,7 @@ write_regs: SREG x29, 216(x1) SREG x30, 224(x1) SREG x31, 232(x1) +#endif csrr x1, CSR_MSCRATCH |