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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-16 13:48:55 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-05-16 13:48:55 -0700 |
| commit | 8ae9de3b4d8987de55dc56164429c9d31668b1bb (patch) | |
| tree | a8d67951aa05c4cbc01a04f91235492cea9ba3fd /debug/programs/entry.S | |
| parent | bb8f7775294e612a8ba91d65d5097b19cb00394a (diff) | |
| parent | 50e52c73766bae4919b83e06e53fde4cb20e2ff2 (diff) | |
| download | riscv-tests-8ae9de3b4d8987de55dc56164429c9d31668b1bb.zip riscv-tests-8ae9de3b4d8987de55dc56164429c9d31668b1bb.tar.gz riscv-tests-8ae9de3b4d8987de55dc56164429c9d31668b1bb.tar.bz2 | |
Merge pull request #47 from riscv/debug-0.13
Debug 0.13 Tests
Diffstat (limited to 'debug/programs/entry.S')
| -rwxr-xr-x | debug/programs/entry.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index e021860..c9e319c 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -30,8 +30,23 @@ handle_reset: la t0, trap_entry csrw mtvec, t0 csrwi mstatus, 0 + + // make sure these registers exist by seeing if either S or U bits + // are set before attempting to zero them out. + csrr t1, misa + addi t2, x0, 1 + slli t2, t2, 20 // U_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + addi t2, x0, 1 + slli t2, t2, 18 // S_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + j 2f +1: csrwi mideleg, 0 csrwi medeleg, 0 +2: csrwi mie, 0 # initialize global pointer |