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authorSandeep Rajendran <41020830+SandeepRajendran@users.noreply.github.com>2020-10-19 13:23:43 -0700
committerGitHub <noreply@github.com>2020-10-19 13:23:43 -0700
commitc4217d88bce9f805a81f42e86ff56ed363931d69 (patch)
tree1d3241c165246142b283271cf344e6c15959617f
parent44b343d191b9154801f712968ac0e1a22b458da0 (diff)
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use registers present on rv32e (#299)
-rw-r--r--isa/rv64ui/fence_i.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/isa/rv64ui/fence_i.S b/isa/rv64ui/fence_i.S
index 2893c5e..e6a6912 100644
--- a/isa/rv64ui/fence_i.S
+++ b/isa/rv64ui/fence_i.S
@@ -24,7 +24,7 @@ sh a1, 2f+2, t0
fence.i
la a5, 2f
-jalr a6, a5, 0
+jalr t1, a5, 0
TEST_CASE( 2, a3, 444, nop )
# test prefetcher hit
@@ -38,7 +38,7 @@ fence.i
.align 6
la a5, 3f
-jalr a6, a5, 0
+jalr t1, a5, 0
TEST_CASE( 3, a3, 777, nop )
TEST_PASSFAIL
@@ -54,9 +54,9 @@ insn:
addi a3, a3, 333
2: addi a3, a3, 222
-jalr a5, a6, 0
+jalr a5, t1, 0
3: addi a3, a3, 555
-jalr a5, a6, 0
+jalr a5, t1, 0
RVTEST_DATA_END