Make HiFiveUnleashed tests clean.

HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.

7 files changed, 14 insertions, 1 deletions

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 1e50272..314a775 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -253,7 +253,7 @@ class MemTest64(SimpleMemoryTest):
 
 class MemTestReadInvalid(SimpleMemoryTest):
     def test(self):
-        bad_address = self.hart.ram - 8
+        bad_address = self.hart.bad_address
         good_address = self.hart.ram + 0x80
 
         self.write_nop_program(2)
diff --git a/debug/targets.py b/debug/targets.py
index be5c9fa..e9fb4f6 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -28,6 +28,10 @@ class Hart:
     ram = None
     ram_size = None
 
+    # Address where we expect memory accesses to fail, usually because there is
+    # no device mapped to that location.
+    bad_address = None
+
     # Number of instruction triggers the hart supports.
     instruction_hardware_breakpoint_count = 0
 
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 913dccf..463e7cf 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -5,6 +5,7 @@ class spike32_hart(targets.Hart):
     xlen = 32
     ram = 0x10000000
     ram_size = 0x10000000
+    bad_address = 0x10000000 - 8
     instruction_hardware_breakpoint_count = 4
     reset_vectors = [0x1000]
     link_script_path = "spike32.lds"
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index ec43a11..cdb67f7 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -5,6 +5,7 @@ class spike64_hart(targets.Hart):
     xlen = 64
     ram = 0x1212340000
     ram_size = 0x10000000
+    bad_address = 0x1212340000 - 8
     instruction_hardware_breakpoint_count = 4
     reset_vectors = [0x1000]
     link_script_path = "spike64.lds"
diff --git a/debug/targets/SiFive/HiFiveUnleashed-flash.py b/debug/targets/SiFive/HiFiveUnleashed-flash.py
index cb2741e..947d061 100644
--- a/debug/targets/SiFive/HiFiveUnleashed-flash.py
+++ b/debug/targets/SiFive/HiFiveUnleashed-flash.py
@@ -4,6 +4,7 @@ class E51(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     link_script_path = "HiFiveUnleashed-flash.lds"
     reset_vectors = [0x1004]
@@ -12,6 +13,7 @@ class U54(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     link_script_path = "HiFiveUnleashed-flash.lds"
     reset_vectors = [0x1004]
@@ -19,4 +21,5 @@ class U54(targets.Hart):
 class HiFiveUnleashedFlash(targets.Target):
     support_hasel = False
     harts = [E51(), U54(), U54(), U54(), U54()]
+    support_memory_sampling = False # Needs SBA
     openocd_config_path = "HiFiveUnleashed.cfg"
diff --git a/debug/targets/SiFive/HiFiveUnleashed.cfg b/debug/targets/SiFive/HiFiveUnleashed.cfg
index 3aa5538..3d20be0 100644
--- a/debug/targets/SiFive/HiFiveUnleashed.cfg
+++ b/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -55,6 +55,7 @@ load_image targets/SiFive/HiFiveUnleashed_setup.bin 0x08000000
 foreach t [target names] {
     targets $t
     reg pc 0x08000000
+    arm semihosting enable
 }
 resume
 wait_halt
diff --git a/debug/targets/SiFive/HiFiveUnleashed.py b/debug/targets/SiFive/HiFiveUnleashed.py
index 9bf7cae..04f6cef 100644
--- a/debug/targets/SiFive/HiFiveUnleashed.py
+++ b/debug/targets/SiFive/HiFiveUnleashed.py
@@ -4,6 +4,7 @@ class E51(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     reset_vectors = [0x1004]
     misa = 0x8000000000101105
@@ -12,10 +13,12 @@ class U54(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 1024 * 1024
+    bad_address = 0x3000000000 + 0x3FFFFFFFFF + 1
     instruction_hardware_breakpoint_count = 2
     reset_vectors = [0x1004]
     misa = 0x800000000014112d
 
 class HiFiveUnleashed(targets.Target):
     support_hasel = False
+    support_memory_sampling = False # Needs SBA
     harts = [E51(), U54(), U54(), U54(), U54()]