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| author | Tim Newsome <tim@sifive.com> | 2017-12-20 15:00:01 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-12-20 15:00:01 -0800 |
| commit | 9eb3b8d3fcc7a491121c186e3a35022e11bb5653 (patch) | |
| tree | 89bd71c87806e26e603f042a83ccdd3d628c621c | |
| parent | 30b70b7ed988fa06ab423e05b272898a1527ba11 (diff) | |
| download | riscv-tests-9eb3b8d3fcc7a491121c186e3a35022e11bb5653.zip riscv-tests-9eb3b8d3fcc7a491121c186e3a35022e11bb5653.tar.gz riscv-tests-9eb3b8d3fcc7a491121c186e3a35022e11bb5653.tar.bz2 | |
Remove `set arch riscv:rv%d`
gdb gets target XLEN from register width now, so this is taken care of
automatically.
| -rw-r--r-- | debug/testlib.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/debug/testlib.py b/debug/testlib.py index 39a6fc4..ce8aeca 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -800,7 +800,6 @@ class GdbTest(BaseTest): self.logs += self.gdb.lognames() self.gdb.connect() - self.gdb.global_command("set arch riscv:rv%d" % self.hart.xlen) self.gdb.global_command("set remotetimeout %d" % self.target.timeout_sec) |