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| author | zhonghochen <zhonghochen@gmail.com> | 2018-12-18 21:16:48 +0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-12-18 15:16:48 +0200 |
| commit | d2b8b97afbc7317cc9d67cf360819935df1efef4 (patch) | |
| tree | efac89828acb96e5dae6583aefb643b1c68f2adb | |
| parent | 3b90c1f894ee4aa78a44c2ecb0cce26e46ef3baa (diff) | |
| download | riscv-tests-d2b8b97afbc7317cc9d67cf360819935df1efef4.zip riscv-tests-d2b8b97afbc7317cc9d67cf360819935df1efef4.tar.gz riscv-tests-d2b8b97afbc7317cc9d67cf360819935df1efef4.tar.bz2 | |
Avoid using t3 and t4 for supporting RV32E (#173)
| -rw-r--r-- | isa/rv64mi/illegal.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index d825c44..5531570 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -134,11 +134,12 @@ synchronous_exception: # Make sure mtval contains either 0 or the instruction word. csrr t2, mbadaddr beqz t2, 1f - lhu t3, 0(t0) - lhu t4, 2(t0) - slli t4, t4, 16 - or t3, t3, t4 - bne t2, t3, fail + lhu t1, 0(t0) + xor t2, t2, t1 + lhu t1, 2(t0) + slli t1, t1, 16 + xor t2, t2, t1 + bnez t2, fail 1: la t1, bad2 |