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| author | Tim Newsome <tim@sifive.com> | 2018-10-31 14:33:27 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-10-31 14:33:27 -0700 |
| commit | 8312d916002aae641cb845c0c6591bbab03b2c92 (patch) | |
| tree | a5c3bace44c55ce4cd8e07bc8d222ef6a7858edf | |
| parent | b3c5d7a07f2a08d11f316c39d6cce5374cdcbfd3 (diff) | |
| download | riscv-tests-8312d916002aae641cb845c0c6591bbab03b2c92.zip riscv-tests-8312d916002aae641cb845c0c6591bbab03b2c92.tar.gz riscv-tests-8312d916002aae641cb845c0c6591bbab03b2c92.tar.bz2 | |
Add HiFive1-flash target configuration.
| -rw-r--r-- | debug/targets/SiFive/HiFive1-flash.lds | 44 | ||||
| -rw-r--r-- | debug/targets/SiFive/HiFive1-flash.py | 15 |
2 files changed, 59 insertions, 0 deletions
diff --git a/debug/targets/SiFive/HiFive1-flash.lds b/debug/targets/SiFive/HiFive1-flash.lds new file mode 100644 index 0000000..e4074be --- /dev/null +++ b/debug/targets/SiFive/HiFive1-flash.lds @@ -0,0 +1,44 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + flash (rxl) : ORIGIN = 0x20400000, LENGTH = 128K + ram (wx) : ORIGIN = 0x80000000, LENGTH = 16K +} + +SECTIONS +{ + flash_text : { + *(.text.entry) + *(.text) + } >flash + + /* data segment */ + .data : { *(.data) } >ram + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >ram + + /* bss segment */ + __bss_start = .; + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >ram + .bss : { *(.bss) } >ram + __bss_end = .; + + __malloc_start = .; + . = . + 512; + + /* End of uninitalized data segement */ + _end = .; +} + +ENTRY(_start) + +ASSERT(_end < 0x80004000, "program is too large") diff --git a/debug/targets/SiFive/HiFive1-flash.py b/debug/targets/SiFive/HiFive1-flash.py new file mode 100644 index 0000000..06dfcfc --- /dev/null +++ b/debug/targets/SiFive/HiFive1-flash.py @@ -0,0 +1,15 @@ +import targets + +# Like HiFive1, but put code in flash + +class HiFive1FlashHart(targets.Hart): + xlen = 32 + ram = 0x80000000 + ram_size = 16 * 1024 + instruction_hardware_breakpoint_count = 2 + misa = 0x40001105 + link_script_path = "HiFive1-flash.lds" + +class HiFive1Flash(targets.Target): + harts = [HiFive1FlashHart()] + openocd_config_path = "HiFive1.cfg" |