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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-06 10:22:20 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-04-06 10:22:20 -0700 |
| commit | f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d (patch) | |
| tree | 1f6535dad39b1cb661cdf6058705004682138593 | |
| parent | 35c6ac438af5086510fe120b575090cf8e9b917b (diff) | |
| download | riscv-tests-f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d.zip riscv-tests-f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d.tar.gz riscv-tests-f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d.tar.bz2 | |
Fix expected misa register value for RV32
| -rw-r--r-- | isa/rv64mi/mcsr.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S index 2eeb14c..4bb0445 100644 --- a/isa/rv64mi/mcsr.S +++ b/isa/rv64mi/mcsr.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN #ifdef __riscv64 TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) #else - TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30) + TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) #endif # Check that mhartid reports 0 |