Merge branch 'priv-1.9'

31 files changed, 320 insertions, 363 deletions

diff --git a/Makefile.in b/Makefile.in
index 58716b8..9129d56 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -9,8 +9,8 @@ all: benchmarks isa
 install: all
 	install -d $(instbasedir)/share/riscv-tests/isa
 	install -d $(instbasedir)/share/riscv-tests/benchmarks
-	install -p -m 644 isa/* $(instbasedir)/share/riscv-tests/isa
-	install -p -m 644 benchmarks/* $(instbasedir)/share/riscv-tests/benchmarks
+	install -p -m 644 `find isa -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/isa
+	install -p -m 644 `find benchmarks -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/benchmarks
 
 benchmarks:
 	mkdir -p benchmarks
diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 60486be..29c1d4d 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -64,13 +64,13 @@ _start:
   li  x30,0
   li  x31,0
 
-  li t0, MSTATUS_PRV1; csrc mstatus, t0    # run tests in user mode
-  li t0, MSTATUS_IE1;  csrs mstatus, t0    # enable interrupts in user mode
+  li t0, MSTATUS_MPP;  csrc mstatus, t0    # run tests in user mode
+  li t0, MSTATUS_MPIE; csrs mstatus, t0    # enable interrupts in user mode
   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
 #ifdef __riscv64
-  csrr t0, mcpuid
+  csrr t0, misa
   # make sure processor supports RV64 if this was compiled for RV64
   bltz t0, 1f
   li a0, 1234
diff --git a/env b/env
-Subproject 566e47ecd223d4a84fd0b349f525f74f3657dfc
+Subproject ef1457fa7a3bf3fd58dadd0f30002828b353e57
diff --git a/isa/Makefile b/isa/Makefile
index d5b0b76..4ff1bd3 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -58,7 +58,7 @@ $$($(1)_pm_tests): $(1)-pm-%: $(1)/%.S
 $(1)_tests += $$($(1)_pm_tests)
 
 $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/vm.c $$< -lc -o $$@
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -lc -o $$@
 $(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 7560dbc..66a0e39 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -4,12 +4,16 @@
 
 rv32mi_sc_tests = \
 	csr \
+	dirty \
 	illegal \
 	ma_fetch \
 	ma_addr \
+	mcsr \
 	scall \
 	sbreak \
+	shamt \
 	timer \
+	wfi \
 
 rv32mi_mc_tests = \
 	ipi \
diff --git a/isa/rv32mi/dirty.S b/isa/rv32mi/dirty.S
new file mode 100644
index 0000000..c1f9d19
--- /dev/null
+++ b/isa/rv32mi/dirty.S
@@ -0,0 +1,10 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#undef VM_SV39
+#define VM_SV39 VM_SV32
+
+#include "../rv64mi/dirty.S"
diff --git a/isa/rv32mi/illegal.S b/isa/rv32mi/illegal.S
index c357ed7..e167c71 100644
--- a/isa/rv32mi/illegal.S
+++ b/isa/rv32mi/illegal.S
@@ -1,8 +1,7 @@
 # See LICENSE for license details.
 
 #include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32M
-#define __MACHINE_MODE
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
 
-#include "../rv64si/illegal.S"
+#include "../rv64mi/illegal.S"
diff --git a/isa/rv32mi/ma_addr.S b/isa/rv32mi/ma_addr.S
index df5099a..7575a3f 100644
--- a/isa/rv32mi/ma_addr.S
+++ b/isa/rv32mi/ma_addr.S
@@ -1,8 +1,7 @@
 # See LICENSE for license details.
 
 #include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32M
-#define __MACHINE_MODE
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
 
-#include "../rv64si/ma_addr.S"
+#include "../rv64mi/ma_addr.S"
diff --git a/isa/rv32mi/mcsr.S b/isa/rv32mi/mcsr.S
new file mode 100644
index 0000000..0d5a5cd
--- /dev/null
+++ b/isa/rv32mi/mcsr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/mcsr.S"
diff --git a/isa/rv32si/shamt.S b/isa/rv32mi/shamt.S
index 615ef68..2c92412 100644
--- a/isa/rv32si/shamt.S
+++ b/isa/rv32mi/shamt.S
@@ -10,12 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV32S
+RVTEST_RV32M
 RVTEST_CODE_BEGIN
 
-  la t0, stvec_handler
-  csrw stvec, t0
-
   # Make sure slli with shamt[4] set is legal.
   TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
 
@@ -24,14 +21,14 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec_handler:
+mtvec_handler:
   # Trapping on test 3 is good.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 2
   bne TESTNUM, t0, fail
 
   # Make sure CAUSE indicates an illegal instructino.
-  csrr t0, scause
+  csrr t0, mcause
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   bne t0, t1, fail
   j pass
diff --git a/isa/rv32mi/wfi.S b/isa/rv32mi/wfi.S
new file mode 100644
index 0000000..d5cb3cb
--- /dev/null
+++ b/isa/rv32mi/wfi.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/wfi.S"
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 1283ec4..a40953e 100644
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -4,12 +4,10 @@
 
 rv32si_sc_tests = \
 	csr \
-	shamt \
 	ma_fetch \
-	illegal \
 	scall \
 	sbreak \
-	ma_addr \
+	wfi \
 
 rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
 
diff --git a/isa/rv32si/ma_addr.S b/isa/rv32si/ma_addr.S
deleted file mode 100644
index 51465a2..0000000
--- a/isa/rv32si/ma_addr.S
+++ /dev/null
@@ -1,7 +0,0 @@
-# See LICENSE for license details.
-
-#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32S
-
-#include "../rv64si/ma_addr.S"
diff --git a/isa/rv32si/illegal.S b/isa/rv32si/wfi.S
index ad5c3b1..8bc9279 100644
--- a/isa/rv32si/illegal.S
+++ b/isa/rv32si/wfi.S
@@ -4,4 +4,4 @@
 #undef RVTEST_RV64S
 #define RVTEST_RV64S RVTEST_RV32S
 
-#include "../rv64si/illegal.S"
+#include "../rv64si/wfi.S"
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 9d90b92..95943b7 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -5,7 +5,7 @@
 rv32ui_sc_tests = \
 	simple \
 	add addi \
-	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
 	and andi \
 	auipc \
 	beq bge bgeu blt bltu bne \
@@ -31,5 +31,6 @@ rv32ui_mc_tests = \
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
 rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
 rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
+rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
 
-spike_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests)
+spike32_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests) $(rv32ui_v_tests)
diff --git a/isa/rv32ui/amoxor_w.S b/isa/rv32ui/amoxor_w.S
new file mode 100644
index 0000000..d4b775f
--- /dev/null
+++ b/isa/rv32ui/amoxor_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoxor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x7ffff800, \
+    li  a1, 0xc0000001; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoxor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ui/jalr.S b/isa/rv32ui/jalr.S
index ebe3731..59f6425 100644
--- a/isa/rv32ui/jalr.S
+++ b/isa/rv32ui/jalr.S
@@ -1,88 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# jalr.S
-#-----------------------------------------------------------------------------
-#
-# Test jalr instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  #-------------------------------------------------------------
-  # Test 2: Basic test
-  #-------------------------------------------------------------
-
-test_2:
-  li  TESTNUM, 2
-  li  x31, 0
-  la  x2, target_2
-
-linkaddr_2:
-  jalr x19, x2, 0
-  nop
-  nop
-
-  j fail
-
-target_2:
-  la  x1, linkaddr_2
-  addi x1, x1, 4
-  bne x1, x19, fail
-
-  #-------------------------------------------------------------
-  # Test 3: Check r0 target and that r31 is not modified
-  #-------------------------------------------------------------
-
-test_3:
-  li  TESTNUM, 3
-  li  x31, 0
-  la  x3, target_3
-
-linkaddr_3:
-  jalr x0, x3, 0
-  nop
-
-  j fail
-
-target_3:
-  bne x31, x0, fail
-
-  #-------------------------------------------------------------
-  # Bypassing tests
-  #-------------------------------------------------------------
-
-  TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
-  TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
-  TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
-
-  #-------------------------------------------------------------
-  # Test delay slot instructions not executed nor bypassed
-  #-------------------------------------------------------------
-
-  TEST_CASE( 7, x1, 4, \
-    li  x1, 1; \
-    la  x2, 1f;
-    jalr x19, x2, -4; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-1:  addi x1, x1, 1; \
-    addi x1, x1, 1; \
-  )
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-RVTEST_DATA_END
+#include "../rv64ui/jalr.S"
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 2be4921..73d6c6c 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -15,9 +15,10 @@ RVTEST_CODE_BEGIN
 
   # Turn on VM with superpage identity mapping
   la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
   csrw sptbr, a1
   sfence.vm
-  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S)
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
   csrs mstatus, a1
   la a1, 1f
   csrw mepc, a1
@@ -27,16 +28,17 @@ RVTEST_CODE_BEGIN
   # Try a faulting store to make sure dirty bit is not set
   li TESTNUM, 2
   li t0, 1
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Load new page table
   li TESTNUM, 3
   la t0, page_table_2
+  srl t0, t0, RISCV_PGSHIFT
   csrw sptbr, t0
   sfence.vm
 
   # Try a non-faulting store to make sure dirty bit is set
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Make sure R and D bits are set
   lw t0, page_table_2
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index c5ccffd..ecb3088 100644
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -1,8 +1,40 @@
 # See LICENSE for license details.
 
+#*****************************************************************************
+# illegal.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal instruction trap.
+#
+
 #include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV64M
-#define __MACHINE_MODE
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  li TESTNUM, 2
+  .word 0
+  j fail
+
+  j pass
+
+  TEST_PASSFAIL
+
+mtvec_handler:
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  csrr t0, mcause
+  bne t0, t1, fail
+  csrr t0, mepc
+  addi t0, t0, 8
+  csrw mepc, t0
+  sret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
 
-#include "../rv64si/illegal.S"
+RVTEST_DATA_END
diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
index 8aca665..7178310 100644
--- a/isa/rv64mi/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -14,7 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # enable interrupts
-  csrs mstatus, MSTATUS_IE
+  csrs mstatus, MSTATUS_MIE
   csrs mie, MIP_MSIP
 
   # get a unique core id
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 0448736..aa5dd85 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -1,8 +1,84 @@
 # See LICENSE for license details.
 
+#*****************************************************************************
+# ma_addr.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ld/st trap.
+#
+
 #include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV64M
-#define __MACHINE_MODE
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  .align 3
+  auipc s0, 0
+
+  # indicate it's a load test
+  li s1, CAUSE_MISALIGNED_LOAD
+
+#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
+  li TESTNUM, testnum; \
+  insn x0, offset(base); \
+  j fail \
+
+  MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
+  MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
+  MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
+  MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
+  MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
+
+#ifdef __riscv64
+  MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
+  MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
+  MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
+
+  MISALIGNED_LDST_TEST(10, ld, s0, 1)
+  MISALIGNED_LDST_TEST(11, ld, s0, 2)
+  MISALIGNED_LDST_TEST(12, ld, s0, 3)
+  MISALIGNED_LDST_TEST(13, ld, s0, 4)
+  MISALIGNED_LDST_TEST(14, ld, s0, 5)
+  MISALIGNED_LDST_TEST(15, ld, s0, 6)
+  MISALIGNED_LDST_TEST(16, ld, s0, 7)
+#endif
+
+  # indicate it's a store test
+  li s1, CAUSE_MISALIGNED_STORE
+
+  MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
+  MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
+  MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
+  MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
+
+#ifdef __riscv64
+  MISALIGNED_LDST_TEST(26, sd, s0, 1)
+  MISALIGNED_LDST_TEST(27, sd, s0, 2)
+  MISALIGNED_LDST_TEST(28, sd, s0, 3)
+  MISALIGNED_LDST_TEST(29, sd, s0, 4)
+  MISALIGNED_LDST_TEST(30, sd, s0, 5)
+  MISALIGNED_LDST_TEST(31, sd, s0, 6)
+  MISALIGNED_LDST_TEST(32, sd, s0, 7)
+#endif
+
+  TEST_PASSFAIL
+
+  .align 3
+mtvec_handler:
+  csrr t0, mcause
+  bne t0, s1, fail
+
+  csrr t0, mepc
+  addi t0, t0, 8
+  csrw mepc, t0
+  sret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
 
-#include "../rv64si/ma_addr.S"
+RVTEST_DATA_END
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index c1e2cd3..2eeb14c 100644
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -13,14 +13,20 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
-  # Check that mcpuid reports RV64
-  TEST_CASE(2, a0, 0x2, csrr a0, mcpuid; srl a0, a0, 62)
+  # Check that mcpuid reports the correct XLEN
+#ifdef __riscv64
+  TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
+#else
+  TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+#endif
 
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
 
-  # Check that mimpid reports UC Berkeley
-  TEST_CASE(4, a0, 0x1, csrr a0, mimpid; sll a0, a0, 48; srl a0, a0, 48)
+  # Check that reading mimpid, marchid, and mvendorid doesn't cause exceptions
+  csrr a0, mimpid
+  csrr a0, marchid
+  csrr a0, mvendorid
 
   # Check that mtvec reports DEFAULT_MTVEC
   TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
diff --git a/isa/rv64mi/timer.S b/isa/rv64mi/timer.S
index b7cc633..4697793 100644
--- a/isa/rv64mi/timer.S
+++ b/isa/rv64mi/timer.S
@@ -24,7 +24,7 @@ RVTEST_CODE_BEGIN
   csrw mtimecmp, a0
   li a0, MIP_MTIP
   csrs mie, a0
-  csrs mstatus, MSTATUS_IE
+  csrs mstatus, MSTATUS_MIE
 
   # advance an LFSR until the timer has fired enough times
   li s0, 1023
@@ -64,7 +64,7 @@ mtvec_handler:
   bgez t0, fail
 
   sll t0, t0, 1
-  addi t0, t0, -2*IRQ_TIMER
+  addi t0, t0, -2*IRQ_M_TIMER
   bnez t0, fail
 
   csrr t0, mtime
diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index 9c5db64..076ea59 100644
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -4,9 +4,7 @@
 
 rv64si_sc_tests = \
 	csr \
-	illegal \
 	ma_fetch \
-	ma_addr \
 	scall \
 	wfi \
 	sbreak \
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index d66b432..d0c6724 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -19,12 +19,10 @@ RVTEST_CODE_BEGIN
   #define scause mcause
   #define sepc mepc
   #define stvec_handler mtvec_handler
-  #undef SSTATUS_PS
-  #define SSTATUS_PS MSTATUS_PRV1
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
 #endif
 
-  csrwi cyclew, 0
-
   csrwi sscratch, 3
   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
@@ -36,10 +34,13 @@ RVTEST_CODE_BEGIN
   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
 
   # Make sure writing the cycle counter causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
   TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+#endif
 
   # jump to user land
-  li t0, SSTATUS_PS
+  li t0, SSTATUS_SPP
   csrc sstatus, t0
   la t0, 1f
   csrw sepc, t0
@@ -47,25 +48,27 @@ RVTEST_CODE_BEGIN
   1:
 
   # Make sure reading status in user mode causes an exception.
-  TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus);
-
-  # Make sure rdcycle is legal in user mode.
-  TEST_CASE(12, x0, 0, rdcycle a0)
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus)
+#else
+  TEST_CASE(11, x0, 0, nop)
+#endif
 
   # Exit by doing a syscall.
-  TEST_CASE(13, x0, 1, scall)
+  TEST_CASE(12, x0, 1, scall)
 
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
 stvec_handler:
-  # Trapping on tests 10, 11, and 13 is usually good news.
+  # Trapping on tests 11 and 12 is usually good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 9
   beq TESTNUM, t0, privileged
   li t0, 10
   beq TESTNUM, t0, privileged
-  li t0, 12
+  li t0, 11
   beq TESTNUM, t0, syscall
 
   # Trapping on other tests is bad news.
diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S
deleted file mode 100644
index 43068b4..0000000
--- a/isa/rv64si/illegal.S
+++ /dev/null
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# illegal.S
-#-----------------------------------------------------------------------------
-#
-# Test illegal instruction trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64S
-RVTEST_CODE_BEGIN
-
-#ifdef __MACHINE_MODE
-  #define sscratch mscratch
-  #define sstatus mstatus
-  #define scause mcause
-  #define sepc mepc
-  #define stvec_handler mtvec_handler
-#endif
-
-  li TESTNUM, 2
-  .word 0
-  j fail
-
-  j pass
-
-  TEST_PASSFAIL
-
-stvec_handler:
-  li t1, CAUSE_ILLEGAL_INSTRUCTION
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S
deleted file mode 100644
index 525e028..0000000
--- a/isa/rv64si/ma_addr.S
+++ /dev/null
@@ -1,103 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# ma_addr.S
-#-----------------------------------------------------------------------------
-#
-# Test misaligned ld/st trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64S
-RVTEST_CODE_BEGIN
-
-#ifdef __MACHINE_MODE
-  #define sscratch mscratch
-  #define sstatus mstatus
-  #define scause mcause
-  #define sepc mepc
-  #define stvec_handler mtvec_handler
-#endif
-
-  la s0, stvec_handler
-
-  # indicate it's a load test
-  li s1, 0
-
-#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
-  li TESTNUM, testnum; \
-  insn x0, offset(base); \
-  j fail \
-
-  MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
-  MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
-  MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
-  MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
-  MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
-
-#ifdef __riscv64
-  MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
-  MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
-  MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
-
-  MISALIGNED_LDST_TEST(10, ld, s0, 1)
-  MISALIGNED_LDST_TEST(11, ld, s0, 2)
-  MISALIGNED_LDST_TEST(12, ld, s0, 3)
-  MISALIGNED_LDST_TEST(13, ld, s0, 4)
-  MISALIGNED_LDST_TEST(14, ld, s0, 5)
-  MISALIGNED_LDST_TEST(15, ld, s0, 6)
-  MISALIGNED_LDST_TEST(16, ld, s0, 7)
-#endif
-
-  # indicate it's a store test
-  li s1, 1
-
-  MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
-  MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
-  MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
-  MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
-
-#ifdef __riscv64
-  MISALIGNED_LDST_TEST(26, sd, s0, 1)
-  MISALIGNED_LDST_TEST(27, sd, s0, 2)
-  MISALIGNED_LDST_TEST(28, sd, s0, 3)
-  MISALIGNED_LDST_TEST(29, sd, s0, 4)
-  MISALIGNED_LDST_TEST(30, sd, s0, 5)
-  MISALIGNED_LDST_TEST(31, sd, s0, 6)
-  MISALIGNED_LDST_TEST(32, sd, s0, 7)
-#endif
-
-  TEST_PASSFAIL
-
-  .align 3
-stvec_handler:
-  bnez s1, test_store
-
-test_load:
-  li t1, CAUSE_MISALIGNED_LOAD
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-test_store:
-  li t1, CAUSE_MISALIGNED_STORE
-  csrr t0, scause
-  bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index 272a9eb..db702d9 100644
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -21,14 +21,21 @@ RVTEST_CODE_BEGIN
   #define stvec_handler mtvec_handler
 #endif
 
-#ifndef __rvc
+  .option norvc
+
+  # Without RVC, the jalr should trap, and the handler will skip ahead.
+  # With RVC, the jalr should not trap, and "j fail" should get skipped.
   li TESTNUM, 2
   li t1, 0
   la t0, 1f
   jalr t1, t0, 2
 1:
+  .option rvc
+  c.j fail
+  c.j 2f
+  .option norvc
   j fail
-#endif
+2:
 
   // This test should pass, since JALR ignores the target LSB
   li TESTNUM, 3
@@ -39,14 +46,17 @@ RVTEST_CODE_BEGIN
   j fail
 1:
 
-#ifndef __rvc
   li TESTNUM, 4
   li t1, 0
-  la t0, 3f
-  jr t0, 3
-3:
+  la t0, 1f
+  jalr t1, t0, 3
+1:
+  .option rvc
+  c.j fail
+  c.j 2f
+  .option norvc
   j fail
-#endif
+2:
 
   j pass
 
@@ -74,7 +84,7 @@ stvec_handler:
   addi t0, t0, -4
   bne t0, a1, fail
 
-  addi a1, a1, 8
+  addi a1, a1, 12
   csrw sepc, a1
   sret
 
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 935b2dd..703de0b 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -19,26 +19,29 @@ RVTEST_CODE_BEGIN
   #define scause mcause
   #define sepc mepc
   #define stvec_handler mtvec_handler
-  #undef CAUSE_SUPERVISOR_ECALL
-  #define CAUSE_SUPERVISOR_ECALL CAUSE_MACHINE_ECALL
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
 #endif
 
   li TESTNUM, 2
+
+  li t0, SSTATUS_SPP
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  eret
+1:
+
   scall
   j fail
 
-  j pass
-
   TEST_PASSFAIL
 
 stvec_handler:
-  li t1, CAUSE_SUPERVISOR_ECALL
+  li t1, CAUSE_USER_ECALL
   csrr t0, scause
   bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
+  j pass
 
 RVTEST_CODE_END
 
diff --git a/isa/rv64si/wfi.S b/isa/rv64si/wfi.S
index 956121a..6b1e818 100644
--- a/isa/rv64si/wfi.S
+++ b/isa/rv64si/wfi.S
@@ -15,15 +15,15 @@ RVTEST_CODE_BEGIN
 
 #ifdef __MACHINE_MODE
   #define sstatus mstatus
-  #define sie mie
   #define sip mip
   #undef MIP_SSIP
   #define MIP_SSIP MIP_MSIP
+  #undef SSTATUS_SIE
+  #define SSTATUS_SIE MSTATUS_MIE
 #endif
 
-  # Make sure wfi doesn't stall if an interrupt is pending
-  csrc sstatus, SSTATUS_IE
-  csrs sie, MIP_SSIP
+  # Make sure wfi doesn't stall if an interrupt is pending, even if masked
+  csrc sstatus, SSTATUS_SIE
   csrs sip, MIP_SSIP
   wfi
 
diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index c821165..210973e 100644
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -19,38 +19,16 @@ RVTEST_CODE_BEGIN
 
 test_2:
   li  TESTNUM, 2
-  li  x31, 0
-  la  x2, target_2
+  li  t0, 0
+  la  t1, target_2
 
+  jalr t0, t1, 0
 linkaddr_2:
-  jalr x19, x2, 0
-  nop
-  nop
-
   j fail
 
 target_2:
-  la  x1, linkaddr_2
-  addi x1, x1, 4
-  bne x1, x19, fail
-
-  #-------------------------------------------------------------
-  # Test 3: Check r0 target and that r31 is not modified
-  #-------------------------------------------------------------
-
-test_3:
-  li  TESTNUM, 3
-  li  x31, 0
-  la  x3, target_3
-
-linkaddr_3:
-  jalr x0, x3, 0
-  nop
-
-  j fail
-
-target_3:
-  bne x31, x0, fail
+  la  t1, linkaddr_2
+  bne t0, t1, fail
 
   #-------------------------------------------------------------
   # Bypassing tests
@@ -64,16 +42,16 @@ target_3:
   # Test delay slot instructions not executed nor bypassed
   #-------------------------------------------------------------
 
-  TEST_CASE( 7, x1, 4, \
-    li  x1, 1; \
-    la  x2, 1f;
-    jalr x19, x2, -4; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-    addi x1, x1, 1; \
-1:  addi x1, x1, 1; \
-    addi x1, x1, 1; \
+  TEST_CASE( 7, t0, 4, \
+    li  t0, 1; \
+    la  t1, 1f; \
+    jr  t1, -4; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+1:  addi t0, t0, 1; \
+    addi t0, t0, 1; \
   )
 
   TEST_PASSFAIL