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author | Megan Wachs <megan@sifive.com> | 2018-04-28 20:38:37 -0700 |
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committer | GitHub <noreply@github.com> | 2018-04-28 20:38:37 -0700 |
commit | 835f252ebe59ef782e96f467462a03754ea87936 (patch) | |
tree | 950e792262543fe60f46adfccce5c3c27aae15e3 | |
parent | bfa3b7d34bca67435d91786a81c9df8963bcccae (diff) | |
parent | 65b4e2e93c7cee0a53143c661e1347363e6d6194 (diff) | |
download | riscv-tests-835f252ebe59ef782e96f467462a03754ea87936.zip riscv-tests-835f252ebe59ef782e96f467462a03754ea87936.tar.gz riscv-tests-835f252ebe59ef782e96f467462a03754ea87936.tar.bz2 |
Merge pull request #132 from riscv/debug-clear-satp
debug: need to clear satp before changing priv
-rwxr-xr-x | debug/gdbserver.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index d085e2e..af9a334 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -881,6 +881,13 @@ class PrivRw(PrivTest): # PMP registers are optional pass + # Ensure Virtual Memory is disabled if applicable (SATP register is not reset) + try: + self.gdb.p("$satp=0") + except testlib.CouldNotFetch: + # SATP only exists if you have S mode. + pass + # Leave the PC at _start, where the first 4 instructions should be # legal in any mode. for privilege in range(4): |