Make tests work with RV32E targets. (#196)

5 files changed, 45 insertions, 27 deletions

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 8c58b6b..3e739f3 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -1081,7 +1081,10 @@ class RegsTest(GdbSingleHartTest):
 
 class WriteGprs(RegsTest):
     def test(self):
-        regs = [("x%d" % n) for n in range(2, 32)]
+        if self.hart.extensionSupported('E'):
+            regs = [("x%d" % n) for n in range(2, 16)]
+        else:
+            regs = [("x%d" % n) for n in range(2, 32)]
 
         self.gdb.p("$pc=write_regs")
         for i, r in enumerate(regs):
diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index 3acd786..3796b3b 100755
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -59,14 +59,17 @@ handle_reset:
 .option pop
 
   # Initialize stack pointer.
+  la    sp, stack_bottom
   # Give each hart STACK_SIZE of stack.
   # Assume hart IDs are contiguous and start at 0.
+  li    t1, STACK_SIZE
   csrr  t0, CSR_MHARTID
+  # Don't use mul instruction because not all harts support it.
   addi  t0, t0, 1
-  li    t1, STACK_SIZE
-  mul   t0, t0, t1
-  la    sp, stack_bottom
-  add   sp, sp, t0
+1:
+  add   sp, sp, t1
+  addi  t0, t0, -1
+  bnez  t0, 1b
 
   # Clear all hardware triggers
   li    t0, ~0
@@ -125,6 +128,7 @@ trap_entry:
   SREG x13, 13*REGBYTES(sp)
   SREG x14, 14*REGBYTES(sp)
   SREG x15, 15*REGBYTES(sp)
+#ifndef RV32E
   SREG x16, 16*REGBYTES(sp)
   SREG x17, 17*REGBYTES(sp)
   SREG x18, 18*REGBYTES(sp)
@@ -141,6 +145,7 @@ trap_entry:
   SREG x29, 29*REGBYTES(sp)
   SREG x30, 30*REGBYTES(sp)
   SREG x31, 31*REGBYTES(sp)
+#endif
 
   csrr a0, mcause
   csrr a1, mepc
@@ -167,6 +172,7 @@ trap_entry:
   LREG x13, 13*REGBYTES(sp)
   LREG x14, 14*REGBYTES(sp)
   LREG x15, 15*REGBYTES(sp)
+#ifndef RV32E
   LREG x16, 16*REGBYTES(sp)
   LREG x17, 17*REGBYTES(sp)
   LREG x18, 18*REGBYTES(sp)
@@ -183,6 +189,7 @@ trap_entry:
   LREG x29, 29*REGBYTES(sp)
   LREG x30, 30*REGBYTES(sp)
   LREG x31, 31*REGBYTES(sp)
+#endif
 
   addi sp, sp, 32*REGBYTES
   mret
diff --git a/debug/programs/regs.S b/debug/programs/regs.S
index 63889dc..cfa1179 100644
--- a/debug/programs/regs.S
+++ b/debug/programs/regs.S
@@ -30,6 +30,7 @@ write_regs:
         SREG    x13, 88(x1)
         SREG    x14, 96(x1)
         SREG    x15, 104(x1)
+#ifndef RV32E
         SREG    x16, 112(x1)
         SREG    x17, 120(x1)
         SREG    x18, 128(x1)
@@ -46,6 +47,7 @@ write_regs:
         SREG    x29, 216(x1)
         SREG    x30, 224(x1)
         SREG    x31, 232(x1)
+#endif
 
         csrr    x1, CSR_MSCRATCH
 
diff --git a/debug/targets.py b/debug/targets.py
index b686b2a..c4bee73 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -136,21 +136,33 @@ class Target(object):
                     prefix=binary_name + "_")
             binary_name = self.temporary_binary.name
             Target.temporary_files.append(self.temporary_binary)
-        march = "rv%dima" % hart.xlen
-        for letter in "fdc":
-            if hart.extensionSupported(letter):
-                march += letter
-        testlib.compile(sources +
-                ("programs/entry.S", "programs/init.c",
-                    "-DNHARTS=%d" % len(self.harts),
-                    "-I", "../env",
-                    "-march=%s" % march,
-                    "-T", hart.link_script_path,
-                    "-nostartfiles",
-                    "-mcmodel=medany",
-                    "-DXLEN=%d" % hart.xlen,
-                    "-o", binary_name),
-                xlen=hart.xlen)
+
+        args = list(sources) + [
+                "programs/entry.S", "programs/init.c",
+                "-DNHARTS=%d" % len(self.harts),
+                "-I", "../env",
+                "-T", hart.link_script_path,
+                "-nostartfiles",
+                "-mcmodel=medany",
+                "-DXLEN=%d" % hart.xlen,
+                "-o", binary_name]
+
+        if hart.extensionSupported('e'):
+            args.append("-march=rv32e")
+            args.append("-mabi=ilp32e")
+            args.append("-DRV32E")
+        else:
+            march = "rv%dima" % hart.xlen
+            for letter in "fdc":
+                if hart.extensionSupported(letter):
+                    march += letter
+            args.append("-march=%s" % march)
+            if hart.xlen == 32:
+                args.append("-mabi=ilp32")
+            else:
+                args.append("-mabi=lp%d" % hart.xlen)
+
+        testlib.compile(args)
         return binary_name
 
 def add_target_options(parser):
diff --git a/debug/testlib.py b/debug/testlib.py
index cd20bdd..5c2366a 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -29,15 +29,9 @@ def find_file(path):
             return relpath
     return None
 
-def compile(args, xlen=32): # pylint: disable=redefined-builtin
+def compile(args): # pylint: disable=redefined-builtin
     cc = os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gcc")
     cmd = [cc, "-g"]
-    if xlen == 32:
-        cmd.append("-march=rv32imac")
-        cmd.append("-mabi=ilp32")
-    else:
-        cmd.append("-march=rv64imac")
-        cmd.append("-mabi=lp64")
     for arg in args:
         found = find_file(arg)
         if found: