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| author | takeoverjp <takeoverjp@gmail.com> | 2019-01-27 04:36:36 +0900 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2019-01-26 11:36:36 -0800 |
| commit | 353b55bc233ef314dd27b547af0a6bdee217b3f4 (patch) | |
| tree | f30e974c2daef5ece50d9b94ef023cbcdc240f04 | |
| parent | 4469fecaaefe273848c46885153dfadeb2ed70ed (diff) | |
| download | riscv-tests-353b55bc233ef314dd27b547af0a6bdee217b3f4.zip riscv-tests-353b55bc233ef314dd27b547af0a6bdee217b3f4.tar.gz riscv-tests-353b55bc233ef314dd27b547af0a6bdee217b3f4.tar.bz2 | |
Fix comments for shift amount. (#177)
| -rw-r--r-- | isa/rv64ui/sll.S | 2 | ||||
| -rw-r--r-- | isa/rv64ui/sra.S | 2 | ||||
| -rw-r--r-- | isa/rv64ui/srl.S | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/isa/rv64ui/sll.S b/isa/rv64ui/sll.S index 257aa9d..8682743 100644 --- a/isa/rv64ui/sll.S +++ b/isa/rv64ui/sll.S @@ -35,7 +35,7 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); - # Verify that shifts only use bottom six bits + # Verify that shifts only use bottom six(rv64) or five(rv32) bits TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); diff --git a/isa/rv64ui/sra.S b/isa/rv64ui/sra.S index 9b359a3..580ae89 100644 --- a/isa/rv64ui/sra.S +++ b/isa/rv64ui/sra.S @@ -35,7 +35,7 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); - # Verify that shifts only use bottom five bits + # Verify that shifts only use bottom six(rv64) or five(rv32) bits TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); diff --git a/isa/rv64ui/srl.S b/isa/rv64ui/srl.S index c1e936a..5ee223f 100644 --- a/isa/rv64ui/srl.S +++ b/isa/rv64ui/srl.S @@ -38,7 +38,7 @@ RVTEST_CODE_BEGIN TEST_SRL( 15, 0x0000000021212121, 14 ); TEST_SRL( 16, 0x0000000021212121, 31 ); - # Verify that shifts only use bottom five bits + # Verify that shifts only use bottom six(rv64) or five(rv32) bits TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); |